Granted Patent B2

US 6,956,757 · App. 09/887,201 · Granted Oct 18, 2005

Abstract

Claims (11)

1. An electronic memory device comprising two or more layers of memory circuitry, each layer comprising circuitry for storing and facilitating retrieval of information and decoding circuitry for addressing specific information within said information storage circuitry, wherein said two or more layers are interconnected by conductors at least some of which are also connected to said decoding circuitry.

2. The memory device of claim 1 wherein only a subset of the conductors are connected to the decoding circuitry.

3. The memory device of claim 1 wherein each layer of memory circuitry comprises:

a first plurality of generally parallel conductors;

a second plurality of generally parallel conductors overlapping and generally orthogonal to said first plurality;

non-linear conductive means interconnecting said first and second pluralities of conductors roughly where they overlap;

decoding circuitry for causing a first voltage on a selected one of the first plurality of conductors to differ from voltages of the others of the first plurality of conductors; and

decoding circuitry for causing a second voltage on a selected one of the second plurality of conductors to differ from the voltages of the others of the second plurality of conductors,

wherein (i) the first and second voltages differ sufficiently to forward bias a non-linear conductive means at any point of overlap therebetween and (ii)

a voltage differential between the non-selected ones of the first plurality of conductors and the non-selected ones of the second plurality of conductors is insufficient to forward bias a non-linear conductive means at any point of overlap therebetween.

4. The memory device of claim 3 wherein said non-linear conductive means are absent at some points of overlap.

Assignments (13)