Non-linear conductor memory
View Patent ↗A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.
1. An electronic memory device comprising:
a. information circuitry for storing and facilitating retrieval of information comprising:
i. a first plurality of generally parallel conductors,
ii. a second plurality of generally parallel conductors overlapping the first plurality of generally parallel conductors,
iii. a plurality of storage locations each disposed proximate to a point of overlap between the first and second pluralities of generally parallel conductors, and
iv. a plurality of nonlinear conductive devices each disposed at a storage location;
b. a plurality of row switches each connected to one of the first plurality of generally parallel conductors;
c. a plurality of column switches each connected to one of the second plurality of generally parallel conductors; and
d. selection circuitry for selecting one of the plurality of row switches and one of the plurality of column switches in order to read from or write to the information circuitry,
wherein the selection circuitry for selecting one of the plurality of row switches comprises circuitry, which comprises a first array of nonlinear conductive elements connected to the plurality of row switches, for increasing the impedance of the non-selected row switches relative to the impedance of the selected row switch.
2. The electronic memory device of claim 1 , wherein each nonlinear conductive element in the first array comprises a diode.
3. The electronic memory device of claim 1 , wherein the selection circuitry for selecting one of the plurality of column switches comprises circuitry for causing the impedance of the non-selected column switches to be greater than the impedance of the selected column switch.
4. The electronic memory device of claim 3 , wherein the circuitry for increasing the impedance of the non-selected column switches relative to the impedance of the selected column switch comprises a second array of nonlinear conductive elements connected to the plurality of column switches.
5. The electronic memory device of claim 4 , wherein each nonlinear conductive element in the second array comprises a diode.
6. The electronic memory device of claim 1 , wherein each of the plurality of row switches comprises an enhancement-mode transistor, an enhancement-mode NMOS transistor, a depletion-mode transistor, a PMOS transistor, or a bipolar transistor.
7. The electronic memory device of claim 6 , wherein each of the plurality of row switches consists essentially of an enhancement-mode transistor, an enhancement-mode NMOS transistor, a depletion-mode transistor, a PMOS transistor, or a bipolar transistor.
8. The electronic memory device of claim 1 , wherein each of the plurality of column switches comprises an enhancement-mode transistor, an enhancement-mode NMOS transistor, a depletion-mode transistor, a PMOS transistor, or a bipolar transistor.
9. The electronic memory device of claim 8 , wherein each of the plurality of column switches consists essentially of an enhancement-mode transistor, an enhancement-mode NMOS transistor, a depletion-mode transistor, a PMOS transistor, or a bipolar transistor.
10. The electronic memory device of claim 1 , wherein at least one of the plurality of nonlinear conductive devices is connected to the first and second pluralities of generally parallel conductors at approximately a point of overlap thereof.
11. The electronic memory device of claim 1 , wherein each of the plurality of nonlinear conductive devices comprises at least one of a diode, a fuse, an antifuse, a phase-change material, a resistance-change material, or a chalcogenide material.
12. An electronic memory device comprising:
a. information circuitry for storing and facilitating retrieval of information comprising:
i. a first plurality of generally parallel conductors,
ii. a second plurality of generally parallel conductors overlapping the first plurality of generally parallel conductors,
iii. a plurality of storage locations each disposed proximate to a point of overlap between the first and second pluralities of generally parallel conductors, and
iv. a plurality of nonlinear conductive devices each disposed at a storage location;
b. a plurality of row switches each connected to one of the first plurality of generally parallel conductors;
c. a plurality of column switches each connected to one of the second plurality of generally parallel conductors;
d. selection circuitry for selecting one of the plurality of row switches and one of the plurality of column switches in order to read from or write to the information circuitry;
e. row decoder circuitry disposed between the plurality of row switches and the first plurality of generally parallel conductors; and
f. column decoder circuitry disposed between the plurality of column switches and the second plurality of generally parallel conductors.
13. The electronic memory device of claim 12 , wherein the row decoder circuitry comprises a third array of nonlinear conductive elements.
14. The electronic memory device of claim 13 , wherein each of the third array of nonlinear conductive elements comprises a diode.
15. The electronic memory device of claim 12 , wherein the column decoder circuitry comprises a fourth array of nonlinear conductive elements.
16. The electronic memory device of claim 15 , wherein each of the fourth array of nonlinear conductive elements comprises a diode.
17. The electronic memory device of claim 1 , wherein at least one of the plurality of row switches or at least one of the plurality of column switches comprises a transistor.
18. The electronic memory device of claim 17 , wherein the transistor is selected from the group consisting of BJT, JFET, MOSFET, FET, TFT, SCR, UJT, triac, vacuum tube, gated field emitter, and MEMS switching devices.
19. A method comprising the steps of:
providing an electronic memory device comprising a grid of memory locations and selection circuitry therefor, the grid comprising a plurality of rows and row switches associated therewith, and a plurality of columns and column switches associated therewith;
applying a pre-charge voltage to the plurality of row switches and the plurality of column switches;
selecting one of the plurality of row switches by discharging the pre-charge voltage on all but the selected row switch;
selecting one of the plurality of column switches by discharging the pre-charge voltage on all but the selected column switch;
applying a row voltage to the plurality of row switches, thereby increasing a voltage on a selected row connected to the selected row switch; and
applying a column voltage to the plurality of column switches, thereby decreasing a voltage on a selected column connected to the selected column switch.
20. The method of claim 19 , wherein a nonlinear conductive device is disposed at the memory location proximate the intersection of the selected row and the selected column, and the step of applying the row voltage and column voltage changes a state of the nonlinear conductive device.
21. The method of claim 19 , wherein a nonlinear conductive device is disposed at the memory location proximate the intersection of the selected row and the selected column, and the step of applying the row voltage and column voltage outputs a state of the nonlinear conductive device.
22. The electronic memory device of claim 1 , wherein the plurality of storage locations is disposed in a first layer and each of the pluralities of row and column switches are disposed in a layer different from the first layer.
23. The electronic memory device of claim 1 , wherein the plurality of row switches, the plurality of column switches, and the plurality of storage locations are disposed in a three-dimensional configuration.