Error correcting memory access means and method
View Patent ↗As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise. The present invention is a means and a method for accessing streams of data stored within a memory device so as to minimize the cost of device testing and thereby the cost of the device itself. By incorporating error-correcting bits in the data stream, the individual data bits need not be tested. Then, by accessing the memory locations so as to avoid having error correcting techniques fail due to common memory device faults, testing costs can be significantly reduced while maintaining high device yields. A sequential access of the memory device will access data bits in a somewhat diagonal path across the two-dimensional array. The key to the present invention is that the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single (or a small number of) row or column line. In a three or more dimensional array, the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single value in a given dimension for which bulk errors are considered likely.
1. A device whereby information is stored in an array having at least two dimensions and said information comprises data bits and error correcting bits such that errors in the data bits can be corrected;
wherein the number of bits within said information, accessed using any given line along a given one dimension of said multi-dimensional storage array on which error correcting is to be performed, is less than or equal to the number of bits that can be corrected given error correcting bits comprised within said information and a corresponding error correcting method employed.
2. The device of claim 1 wherein the number of bits within said information accessed using any given line along a given one dimension of said multi-dimensional storage array is less than or equal to half the number of bits that can be corrected.
3. A device whereby information is stored in an array having at least two dimensions and said information comprises data bits and error correcting bits such that errors in the data bits can be corrected;
wherein the number of data bits within said information, accessed using any given row or column line along any one dimension of said multi-dimensional storage array, is less than or equal to the number of bits that can be corrected given an error correcting method employed and the corresponding error correcting bits comprised within said information.
4. The device of claim 3 wherein a portion of the data storage is removable or interchangeable.
5. The device of claim 3 wherein the number of bits within said information accessed using any given row or column line along any one dimension of said multi-dimensional storage array is less than or equal to half the number of bits that can be corrected.
6. A method for accessing data comprising error correcting bits whereby said method comprises the step of advancing the sub-address on an address decoder for lines in one or more dimensions such that the number of bits accessed in any portion of the array is less than or equal to the number of bits that can be corrected by said error correcting bits and corresponding error correcting algorithm.
7. The method of claim 6 whereby said advancing of the sub-address on an address decoder occurs on the address decoder for more than one of the dimensions of the storage array.
8. The method of claim 6 whereby said advancing is done sequentially.
9. The method of claim 6 whereby said advancing is done by a pseudo-random address generator.
10. The method of claim 6 wherein the number of bits accessed in any portion of the array is less than or equal to half the number of bits that can be corrected.