NMOS regulated voltage reference
View Patent ↗A method and system for generating a reference voltage are disclosed. The reference voltage is generated by generating a voltage VRIGHT using a first transistor and generating a voltage VBIAS using a second transistor. The gates of the two transistors are connected to a common node VREF, but the loads of the transistors have different resistances. At least one differential pair is used to detect a difference between voltages VRIGHT and VBIAS. VREF is forced to a value at which the source-drain currents in each of the transistors is equal. The transistors sued are NMOS transistors.
1. A system for generating a reference voltage, the system comprising only NMOS transistors or resistors and capacitors:
a first transistor for generating a voltage VRIGHT on its source and having a first load;
a second transistor for generating a voltage VBIAS on its source and having a second load, wherein the gates of the first and second transistor are connected to a common node VREF, and wherein the first and second loads comprise different resistances; and
at least one differential pair for detecting a difference between voltages VRIGHT and VBIAS and generating a signal related to the difference, wherein the signal related to the difference is connected to VREF, thereby forcing VREF to a value at which the source-drain currents in each of the first and second transistors are equal and wherein all the transistors are NMOS.
2. The system of claim 1 , wherein the at least one differential pair comprises a single differential pair, two stages of differential pairs, or there stages of differential pairs.
3. The system of claim 1 , wherein the first load or the second load comprises a resistor R.
4. The system of claim 1 , wherein the at least one differential pair generates the signal with an output resistor R 0 .
5. The system of claim 4 , wherein R 0 is sized larger for greater gain or smaller for greater feedback.
6. A method for generating a reference voltage using only NMOS transistors or resistors and capacitors, the method comprising:
generating a voltage VRIGHT using a first transistor having a first load;
generating a voltage VBIAS using a second transistor having a second load, wherein the gates of the first and second transistor are connected to a common node VREF, and wherein the first and second loads comprise different resistances;
detecting a difference between the voltages VRIGHT and VBIAS using at least one differential pair and generating a single related to the difference; and
forcing VREF to a value at which the source-drain currents in each of the first and second transistors are equal using only NMOS transistors.
7. The method of claim 6 , further comprising generating the single related to the difference with an output resistor R 0 .
8. The method of claim 7 , further comprising sizing R 0 larger for greater gain or smaller for greater feedback.