Diagonally accessed memory array circuit
View Patent ↗A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.
1. A memory device comprising:
one or more memory arrays each comprising a plurality of memory storage locations;
an address input for receiving a memory address to be transformed into a physical address within the one or more memory arrays;
a row address decoder/selector configured to select one or more physical-address locations within the one or more memory arrays along a first dimension;
a column address decoder/selector configured to select one or more physical-address locations within the one or more memory arrays along a second dimension different from the first dimension; and
transforming logic configured to (i) transform a first portion of the address received at the address input, thereby forming a transformed address portion, and (ii) direct the transformed address portion to the row address decoder/selector,
wherein (i) the row address decoder/selector selects physical-address locations based on the transformed address portion and a second portion of the address different from the first portion, (ii) the column address decoder/selector selects physical-address locations based on the first portion of the address, and (iii) the physical-address locations selected by the row address decoder/selector and the column address decoder/selector fall along a generally diagonal path within the one or more memory arrays.
2. The memory device of claim 1 , wherein the transforming logic comprises at least one of adder logic, exclusive-or logic, or comparator logic.
3. The memory device of claim 2 , wherein (i) the transforming logic comprises adder logic utilizing an overflow carry bit, and (ii) the overflow carry bit is not used or is ignored.
4. The memory device of claim 1 , wherein the one or more memory arrays are programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.
5. The memory device of claim 1 , wherein the row address decoder/selector, the column address decoder/selector, and the one or more memory arrays are disposed within a removable memory storage device.
6. The memory device of claim 1 , wherein at least one of the memory storage locations comprises a programmable material.
7. The memory device of claim 6 , wherein the programmable material comprises a phase-change material.
8. The memory device of claim 7 , wherein the phase-change material comprises a chalcogenide material.
9. The memory device of claim 6 , wherein the programmable material is reprogrammable or erasable.
10. The memory device of claim 1 , wherein at least one of the memory storage locations comprises a non-linear device.
11. The memory device of claim 10 , wherein the non-linear device comprises a transistor.
12. The memory device of claim 10 , wherein the non-linear device comprises a diode.
13. The memory device of claim 10 , wherein the non-linear device conducts current better in one direction than the other for a given applied voltage.
14. The memory device of claim 1 , wherein at least one of the memory storage locations is one-time programmable.
15. The memory device of claim 1 , wherein at least one of the memory storage locations comprises a fuse.
16. The memory device of claim 1 , wherein at least one of the memory storage locations comprises an antifuse.
17. The memory device of claim 1 , or more arrays of memory storage locations comprises arrangement of said arrays wherein the one or more memory arrays are arranged in at least one of tiles or layers.
18. The memory device of claim 1 , further comprising an address holding circuit configured to receive the memory address from the address input and direct the memory address to the row address decoder/selector, the column address decoder/selector, and the transforming logic, the address holding circuit comprising at least one of a latch, a counter, or an incrementer.
19. A method of accessing a memory device comprising one or more memory arrays each comprising a plurality of memory storage locations, the method comprising:
receiving a memory address to be transformed into a physical address within the one or more memory arrays;
transforming a first portion of the received address, thereby forming a transformed address portion;
selecting physical-address locations within the one or more memory arrays along a first dimension based on the transformed address portion and a second portion of the received address different from the first portion; and
selecting physical-address locations within the one or more memory arrays along a second dimension based on the first portion of the received address,
wherein the selected physical-address locations fall along a generally diagonal path within the one or more memory arrays.