Embedded non-volatile memory
View Patent ↗The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
1. A CMOS device, comprising:
a doped silicon substrate;
doped epi silicon layer formed over the doped silicon substrate;
a p doped well disposed within the doped epi silicon layer; and
a non-volatile memory array coupled to the p doped well.
2. The CMOS device of claim 1 , wherein the memory array includes diodes.
3. The CMOS device of claim 1 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
4. A CMOS device, comprising:
a doped silicon substrate;
doped epi silicon layer formed over the doped silicon substrate;
a p doped well disposed within the doped epi silicon layer; and
a non-volatile memory array coupled to the p doped well, wherein the memory array includes diodes, wherein the diodes comprise epi-silicon.
5. The CMOS device of claim 4 , wherein the non-volatile memory array includes a phase-change material.
6. The CMOS device of claim 5 , wherein the phase-change material comprises a Chalcogenide alloy.
7. The CMOS device of claim 6 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
8. The CMOS device of claim 5 , wherein the phase-change material comprises one or more of germanium, tellurium and antimony.
9. The CMOS device of claim 8 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
10. A CMOS device, comprising:
a doped silicon substrate;
doped epi silicon layer formed over the doped silicon substrate;
a p doped well disposed within the doped epi silicon layer; and
a non-volatile memory array coupled to the p doped well, wherein the memory array includes diodes, wherein the diodes comprise poly-silicon.
11. The CMOS device of claim 10 , wherein the non-volatile memory array includes a phase-change material.
12. The CMOS device of claim 11 , wherein the phase-change material comprises a Chalcogenide alloy.
13. The CMOS device of claim 12 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
14. The CMOS device of claim 11 , wherein the phase-change material comprises one or more of germanium, tellurium and antimony.
15. The CMOS device of claim 14 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
16. A CMOS device, comprising:
a doped silicon substrate;
doped epi silicon layer formed over the doped silicon substrate;
a p doped well disposed within the doped epi silicon layer; and
a non-volatile memory array coupled to the p doped well, wherein the non-volatile memory array includes a phase-change material.
17. The CMOS device of claim 16 , wherein the phase-change material comprises a Chalcogenide alloy.
18. The CMOS device of claim 17 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.
19. The CMOS device of claim 16 , wherein the phase-change material comprises one or more of germanium, tellurium and antimony.
20. The CMOS device of claim 19 , wherein the substrate is P + doped and wherein the doped epi silicon layer is P − doped.