Low-cost high-density rectifier matrix memory
View Patent ↗A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
1. An electronic memory device comprising a plurality of layers of circuitry, wherein:
a first layer comprises (i) storage circuitry for storing and facilitating retrieval of information and
(ii) non-storage circuitry contributing to the access of the storage circuitry; and
a substrate layer, disposed beneath the first layer, comprises a plurality of transistors which receive signals from the first layer.
2. The electronic memory device of claim 1 , wherein the first layer is connected to the substrate layer by conductive vias.
3. The electronic memory device of claim 1 , wherein the transistors are NMOS transistors.
4. The electronic memory device of claim 1 , wherein the transistors are PMOS transistors.
5. The electronic memory device of claim 1 , further comprising one or more additional layers.
6. The electronic memory device of claim 1 , wherein the storage circuitry for storing and facilitating retrieval of information comprises:
a first plurality of generally parallel conductors;
a second plurality of generally parallel conductors overlapping and generally orthogonal to the first plurality of generally parallel conductors; and
a plurality of nonlinear conductive devices, each device located proximate to a point of overlap between the first and second pluralities of generally parallel conductors.
7. The electronic memory device of claim 6 , wherein at least one of the plurality of nonlinear conductive devices is connected to the second plurality of generally parallel conductors proximate to the point of overlap between the first and second pluralities of generally parallel conductors.
8. The electronic memory device of claim 1 , wherein the storage circuitry comprises a programmable device.
9. The electronic memory device of claim 8 , wherein the programmable device comprises a phase-change material.
10. The electronic memory device of claim 9 , wherein the phase-change material comprises a chalcogenide alloy.
11. The electronic memory device of claim 1 , wherein the storage circuitry comprises one of a fusible link and an antifusible link.
12. The electronic memory device of claim 6 , wherein each of the plurality of nonlinear conductive devices comprises a programmable element.
13. The electronic memory device of claim 1 , wherein the non-storage circuitry comprises circuitry for precharging the gate of a transistor.
14. The electronic memory device of claim 1 , wherein the non-storage circuitry comprises circuitry for discharging the gate of a transistor.
15. The electronic memory device of claim 1 , wherein the non-storage circuitry comprises circuitry for address decoding.
16. The electronic memory device of claim 1 , wherein the non-storage circuitry comprises circuitry for output sensing.
17. An electronic memory device comprising a plurality of layers of circuitry, wherein:
a first layer comprises (i) storage circuitry for storing and facilitating retrieval of information comprising:
(a) a first plurality of generally parallel conductors;
(b) a second plurality of generally parallel conductors overlapping and generally orthogonal to the first plurality of generally parallel conductors; and
(c) a plurality of nonlinear conductive devices, each device connected to the first plurality of generally parallel conductors at approximately a point of overlap between the first and second pluralities of generally parallel conductors, and
(ii) non-storage circuitry contributing to the access of the storage circuitry; and
a substrate layer, disposed beneath the first layer, comprises a plurality of transistors which receive signals from the non-storage circuitry,
wherein each of the plurality of nonlinear conductive devices comprises a fuse, an antifuse, or a phase-change material.