Solid state devices having fine pitch structures
View Patent ↗In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
1. A method for forming an array, the method comprising:
forming a plurality of rows of hardmask material above one or more layers of insulating material;
forming a plurality of columns of hardmask material above the plurality of rows of hardmask material;
etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material; and
forming memory cells in the holes,
wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step,
wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows; and
wherein the first subset of the plurality of rows are separated by a distance corresponding to at least double a distance between array bitlines.
2. The method of claim 1 , wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material.
3. The method of claim 1 , wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step.
4. The method of claim 3 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.
5. The method of claim 1 , wherein etching the holes comprises performing a selective etch of the insulating material, wherein the insulating material comprises at least two different types of insulating materials, and wherein the selectively etched hole comprises a first diameter etched in a first type of insulating material and a second diameter larger than the first diameter etched in a second type of insulating material.
6. The method of claim 1 , further comprising forming an electronic circuit in electrical communication with the array.
7. An electronic circuit in the form of an array comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows:
wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines.
8. The electronic circuit of claim 7 , wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material.
9. The electronic circuit of claim 7 , wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step.
10. The electronic circuit of claim 9 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.
11. The electronic circuit of claim 7 , wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step.
12. The electronic circuit of claim 11 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.
13. An electronic system comprising one or more array circuits, the array circuits comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows;
wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines.
14. The electronic system of claim 13 , wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material.
15. The electronic system of claim 13 , wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step.
16. The electronic system of claim 15 , wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step.
17. The electronic system of claim 16 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.
18. The electronic system of claim 15 , wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step.
19. The electronic system of claim 18 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.
20. The electronic circuit of claim 13 , wherein the holes in which memory cells are formed have corners and these corners are rounded.