Bipolar-MOS memory circuit
View Patent ↗Electronic memory circuits, and more particularly, low power electronic memory circuits having low manufacturing costs are disclosed. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
1. An electronic memory device comprising:
control logic for controlling one or more information storage arrays, the control logic comprising:
(A) one or more NMOS transistors, one or more PNP bipolar transistors, and no PMOS transistors, wherein each PNP bipolar transistor has (i) a base electrically coupled to an NMOS transistor, (ii) an emitter, and (iii) a collector through which a line of an information storage array is energized in response to switching of the NMOS transistor; or
(B) one or more PMOS transistors, one or more NPN bipolar transistors, and no NMOS transistors, wherein each NPN bipolar transistor has (i) a base electrically coupled to a PMOS transistor, (ii) an emitter, and (iii) a collector through which a line of an information storage array is energized in response to switching of the PMOS transistor.
2. The electronic memory device of claim 1 , wherein (i) the control logic comprises one or more NMOS transistors, one or more PNP bipolar transistors, and no PMOS transistors, and (ii) each NMOS transistor is configured to pull the base of a PNP bipolar transistor to a low voltage state.
3. The electronic memory device of claim 1 , wherein (i) the control logic comprises one or more PMOS transistors, one or more NPN bipolar transistors, and no NMOS transistors, and (ii) each PMOS transistor is configured to pull the base of a NPN bipolar transistor to a high voltage state.
4. The electronic memory device of claim 1 , further comprising one or more information storage arrays each having (i) a plurality of word lines, (ii) a plurality of bit lines intersecting the plurality of word lines, and (iii) a plurality of storage locations each disposed proximate a point of intersection between a word line and a bit line, wherein each word line is electronically coupled to a PNP bipolar transistor or an NPN bipolar transistor.
5. The electronic memory device of claim 4 , further comprising a non-linear conductor disposed at least at one storage location.
6. The electronic memory device of claim 5 , wherein the non-linear conductor comprises a diode, a base-emitter junction of a bipolar transistor, a base-collector junction of a bipolar transistor, or a vertical MOS transistor.
7. The electronic memory device of claim 1 , wherein the control logic comprises a plurality of NMOS transistors and a plurality of PNP bipolar transistors, further comprising an address decoder coupled to the plurality of NMOS transistors.