Memory array with readout isolation
View Patent ↗Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.
1. An information-storage circuit comprising:
a first set of generally parallel conductive lines;
a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;
a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap; and
output-detection circuitry for determining a selected bit state without interference from external loading.
2. The circuit of claim 1 wherein the output-detection circuitry determines the selected bit state by measuring charge.
3. The circuit of claim 2 further comprising a plurality of capacitances, wherein each measured charge is stored on a capacitance.
4. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.
5. The circuit of claim 4 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.
6. The circuit of claim 1 further comprising a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.
7. The circuit of claim 1 wherein the output-detection circuitry comprises a capacitive switching circuit.
8. The circuit of claim 1 wherein the circuit is electrically connected to an external device, and said electrical connection induces a loading effect.
9. The circuit of claim 8 wherein the output-detection circuitry further comprises a comparator in the external device.
10. The circuit of claim 9 wherein the comparator is operated synchronously with the information-storage circuit.
11. The circuit of claim 9 wherein the comparator detects a change in at least one of charge, voltage and current to determine a digital output state.
12. The circuit of claim 1 wherein the nonlinear element is selected from the group consisting of a diode, a series combination of a diode and a contact opening, and a series combination of a diode and a one-time programmable element.
13. A method for accessing an information-storage circuit without interference from external loading effects, the method comprising:
providing a first set of generally parallel conductive lines;
providing a second set of generally parallel conductive lines that is generally perpendicular to and overlapping with the first set of lines;
providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a nonlinear element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap; and
providing output-detection circuitry for determining a selected bit state without interference from external loading.
14. The method of claim 13 wherein providing output-detection circuitry comprises providing output-detection circuitry that determines the selected bit state by measuring charge.
15. The method of claim 14 further comprising providing a plurality of capacitances, wherein each measured charge is stored on a capacitance.
16. The method of claim 13 further comprising providing a plurality of capacitances, wherein each capacitance is associated with one of said nonlinear elements.
17. The method of claim 16 wherein each capacitance occurs between one of said nonlinear elements and one line selected from said first set of lines or said second set of lines.
18. The method of claim 13 further comprising providing a plurality of capacitances, wherein each capacitance occurs between a first line from said first set of lines and a second line from said second set of lines.
19. The method of claim 13 wherein providing output-detection circuitry comprises providing output-detection circuitry comprising a capacitive switching circuit.
20. The method of claim 13 further comprising electrically connecting the circuit to an external device, and said electrical connection induces a loading effect.
21. The method of claim 20 wherein providing output-detection circuitry comprises providing output-detection circuitry comprising a comparator in the external device.
22. The method of claim 21 wherein the comparator is operated synchronously with the information-storage circuit.
23. The method of claim 21 further comprising detecting a change using the comparator in at least one of charge, voltage and current to determine a digital output state.
24. The method of claim 13 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a diode bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.
25. The method of claim 13 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a series combination of a diode and a contact opening bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.
26. The method of claim 13 wherein providing a plurality of bit states comprises providing a plurality of bit states, with each bit state of said plurality occurring in the general vicinity of a region of overlap between a line from the first set of lines and a line from the second set of lines, and the state of any bit state being determined by the presence or absence of a series combination of a diode and a one-time programmable element bridging a line from the first set of lines and a line from the second set of lines at a region of overlap.