SCR matrix storage device
View Patent ↗One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others.
1. A method of forming a storage matrix, the method comprising:
forming a first plurality of intersection points at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, each non-linear element determining a bit state for the corresponding intersection point, and exhibiting, at a given voltage and independent of the bit state for its corresponding intersection point, a first current level or a second current level greater than the first current level, the non-linear element exhibiting the second current level at the given voltage only if the non-linear element has been subjected to a voltage at least equal to the threshold,
wherein during selection a selected non-linear element is subjected to a voltage at least equal to the threshold and the unselected non-linear elements are subjected to a voltage less than the threshold.
2. The method of claim 1 , further comprising providing address circuitry for determining the bit state at each intersection point.
3. The method of claim 1 , wherein at least some of the non-linear elements are semiconductor controlled rectifiers without gate control connections thereto.
4. The method of claim 1 , wherein at least some of the non-linear elements are ferroelectric Schottky diodes.
5. The method of claim 1 , wherein the storage matrix is a read-only memory.
6. The method of claim 1 , wherein the storage matrix is a one-time programmable read-only memory.
7. The method of claim 1 , wherein the storage matrix is a multiple read-write memory.
8. The method of claim 1 , further comprising:
forming a second plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements, disposed above the first plurality of intersection points; and
connecting the second plurality of intersection points to the first plurality of intersection points with at least one via.
9. A method of manipulating information, the method comprising the steps of:
providing a plurality of intersection points at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, each non-linear element determining a bit state for the corresponding intersection point, and exhibiting, at a given voltage and independent of the bit state for its corresponding intersection point, a first current level or a second current level greater than the first current level, the non-linear element exhibiting the second current level at the given voltage only if the non-linear element has been subjected to a voltage at least equal to the threshold; and
selecting an intersection point.
10. The method of claim 9 , wherein selecting the intersection point comprises enabling a row comprising the intersection point and enabling a column comprising the intersection point.
11. The method of claim 10 , wherein enabling the row comprises increasing a voltage thereon and enabling the column comprises decreasing a voltage thereon.
12. The method of claim 9 , wherein selecting an intersection point comprises applying a voltage exceeding the threshold to a non-linear element bridging the selected intersection point.
13. The method of claim 9 , wherein selecting an intersection point comprises applying a voltage less than the threshold to non-linear elements not at the selected intersection point.
14. The method of claim 9 , further comprising determining a bit state of the selected intersection point.