SCR matrix storage device
View Patent ↗In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, as well as, disposed at each intersection point bridged by a non-linear element, a programmable material in series with the non-linear element and determining a bit state for the corresponding intersection point.
1. An addressable storage matrix facilitating control over excessive current leakage, the matrix comprising:
a first plurality of intersection points at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, each non-linear element exhibiting, at a given voltage and independent of the bit state for its corresponding intersection point, a first current level or a second current level greater than the first current level, the non-linear element exhibiting the second current level at the given voltage only if the non-linear element has been subjected to a voltage at least equal to the threshold; and
disposed at each intersection point bridged by a two-terminal non-linear element, a programmable material in series with the two-terminal non-linear element and determining a bit state for the corresponding intersection point.
2. The addressable storage matrix of claim 1 , wherein each non-linear element is selectable by subjection to a voltage at least equal to the threshold.
3. The addressable storage matrix of claim 1 , further comprising address circuitry for determining the bit state at each intersection point.
4. The addressable storage matrix of claim 1 , wherein at least some of said non-linear elements are semiconductor controlled rectifiers without gate control connections thereto.
5. The addressable storage matrix of claim 1 , wherein at least some of said non-linear elements are ferroelectric Schottky diodes.
6. The addressable storage matrix of claim 1 , wherein the storage matrix is a read-only memory.
7. The addressable storage matrix of claim 1 , wherein the storage matrix is a one-time programmable read-only memory.
8. The addressable storage matrix of claim 1 , wherein the storage matrix is a multiple read-write memory.
9. The addressable storage matrix of claim 1 , further comprising a second plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements and a second programmable material in series therewith, disposed above the first plurality of intersection points and connected to the first plurality of intersection points by at least one via.
10. The addressable storage matrix of claim 1 , wherein the programmable material comprises a phase change material.
11. The addressable storage matrix of claim 1 , wherein the programmable material comprises an organic material.
12. The addressable storage matrix of claim 1 , wherein the programmable material comprises a magnetic RAM cell.
13. The addressable storage matrix of claim 1 , wherein the programmable material comprises at least one of a molecular transistor or a molecular switch.
14. The addressable storage matrix of claim 1 , wherein the programmable material comprises a nanotube electromechanical switch.
15. A method of forming a storage matrix, the method comprising:
providing a first plurality of intersection points at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, each non-linear element exhibiting, at a given voltage and independent of the bit state for its corresponding intersection point, a first current level or a second current level greater than the first current level, the non-linear element exhibiting the second current level at the given voltage only if the non-linear element has been subjected to a voltage at least equal to the threshold; and
providing, at each intersection point bridged by a two-terminal non-linear element, a programmable material in series with the two-terminal non-linear element and determining a bit state for the corresponding intersection point.
16. The method of claim 15 , wherein each non-linear element is selectable by subjection to a voltage at least equal to the threshold.
17. The method of claim 15 , further comprising providing address circuitry for determining the bit state at each intersection point.
18. The method of claim 15 , wherein at least some of the non-linear elements are semiconductor controlled rectifiers without gate control connections thereto.
19. The method of claim 15 , wherein at least some of the non-linear elements are ferroelectric Schottky diodes.
20. The method of claim 15 , wherein the storage matrix is a read-only memory.
21. The method of claim 15 , wherein the storage matrix is a one-time programmable read-only memory.
22. The method of claim 15 , wherein the storage matrix is a multiple read-write memory.
23. The method of claim 15 , further comprising:
providing a second plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements and a second programmable material in series therewith, disposed above the first plurality of intersection points; and
connecting the second plurality of intersection points to the first plurality of intersection points with at least one via.
24. The method of claim 15 , wherein the programmable material comprises a phase change material.
25. The method of claim 15 , wherein the programmable material comprises an organic material.
26. The method of claim 15 , wherein the programmable material comprises a magnetic RAM cell.
27. The method of claim 15 , wherein the programmable material comprises at least one of a molecular transistor or a molecular switch.
28. The method of claim 15 , wherein the programmable material comprises a nanotube electromechanical switch.