Method for forming self-aligned phase-change semiconductor diode memory
View Patent ↗A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks.
1. A method for forming a non-volatile rewritable memory device, the method comprising:
over a conductive material, forming pillars of material surrounded by isolating material;
forming substantially coplanar top surfaces of the pillars and the isolating material;
at a first plurality of pillar locations, simultaneously etching the pillar material and the isolating material, the pillar material being etched at a greater rate than the isolating material to form recesses over the pillars;
at the first plurality of pillar locations, filling the recesses and forming circuit elements including the filled recesses, each circuit element comprising a rectifying junction;
at a second plurality of pillar locations different from the first plurality of pillar locations, simultaneously etching the pillar material and the isolating material, the pillar material being (i) etched at a greater rate than the isolating material and (ii) at least partially removed to form recesses;
at the second plurality of pillar locations, filling the recesses with a conductor to form pillars each having an ohmic conductive path to the underlying conductive material; and
over at least the second plurality of pillar locations, forming a layer of a second conductive material, the pillars in the second plurality of pillar locations forming via-connections between the second conductive material and the underlying conductive material.
2. The method of claim 1 , wherein the substantially coplanar top surfaces are formed by polishing.
3. The method of claim 1 , wherein the circuit elements comprise a non-volatile memory cell.
4. The method of claim 1 , wherein the circuit elements comprise a diode.
5. The method of claim 1 , wherein etching at the first plurality of pillar locations comprises reactive-ion etching.
6. The method of claim 5 , wherein reactive-ion etching comprises chlorine etching.
7. The method of claim 1 , wherein the pillars of material comprise at least one of silicon, amorphous silicon, or polysilicon.
8. The method of claim 7 , wherein forming the pillars of material comprises epitaxial deposition.
9. The method of claim 1 , wherein the isolating material consists essentially of a dielectric.
10. The method of claim 1 , further comprising, at a third plurality of pillar locations different from both the first and second pluralities of pillar locations, forming a rectifying junction within each pillar.
11. The method of claim 10 , wherein the rectifying junctions within pillars in the third plurality of pillar locations are formed by dopant implantation.
12. The method of claim 1 , wherein the rectifying junctions at the first plurality of pillar locations are formed by dopant implantation.
13. A method for fabricating an electronic device, the method comprising:
forming an array of pillars over a conductive material, each pillar comprising a diode material and being substantially surrounded by an insulating material;
planarizing the array of pillars to expose a top surface of each pillar;
at a first plurality of pillar locations, removing an upper portion of each pillar to form a recess thereover; and
forming a phase-change material within each recess in the first plurality of pillar locations;
at a second plurality of pillar locations different from the first plurality of pillar locations, removing at least an upper portion of each pillar to form a recess;
forming a conductor within each recess in the second plurality of pillar locations, to thereby form pillars each forming an ohmic conductive path to the underlying conductive material; and
over at least the second plurality of pillar locations, forming a layer of a second conductive material, the pillars in the second plurality of pillar locations forming via-connections between the second conductive material and the underlying conductive material.
14. The method of claim 13 , wherein each pillar comprises an etch-stop layer, and the step of removing an upper portion of each pillar in the first plurality of pillar locations comprises exposing the etch-stop layer.
15. The method of claim 13 , wherein the phase-change material comprises a chalcogenide alloy.
16. The method of claim 13 , further comprising forming a spacer within each recess in the first plurality of pillar locations before forming the phase-change material.
17. The method of claim 16 , wherein the spacer comprises an insulating material.
18. The method of claim 13 , wherein the diode material comprises silicon.