IP Library Granted Patent US 10,008,542
Granted Patent B2
US 10,008,542 · App. 15/181,551 · Granted Jun 26, 2018

Solid state devices having fine pitch structures

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Quick Facts
Patent No.
US 10,008,542
App. No.
15/181,551
Granted
Jun 26, 2018
Kind
B2
Abstract

In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Claims (10)

1. A method for forming an array, the method comprising:

forming a plurality of rows of hardmask material above one or more layers of insulating material;

forming a plurality of columns of hardmask material above the plurality of rows of hardmask material;

etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material; and

forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows, wherein etching the holes comprises performing a selective etch of the insulating material, wherein the insulating material comprises at least two different types of insulating materials, and wherein the selectively etched hole comprises a first diameter etched in a first type of insulating material and a second diameter larger than the first diameter etched in a second type of insulating material.

2. The method of claim 1 , further comprising forming an electronic circuit in electrical communication with the array.

3. The method of claim 1 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.

4. The method of claim 1 , wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material.

5. The method of claim 1 , wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step.

6. The method of claim 5 , wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step.

Assignments (12)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2018
From: HGST, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046939/0587 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2016
From: CONTOUR SEMICONDUCTOR, INC.
To: HGST, INC.
Reel/Frame 038908/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2016
From: SHEPARD, DANIEL R.
To: CONTOUR SEMICONDUCTOR, INC.
Reel/Frame 038908/0838 →