INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES
A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.
1 . A method of error correction in a cross point memory device having a data block arranged in a rectangular pattern, comprising:
determining that a number in an individual storage location is incorrect;
subtracting the incorrect individual number from the from the data block; and
inserting a new number into the data block from which the incorrect individual number has been removed.
2 . The method of claim 1 , further comprising:
calculating a difference between the incorrect number in the individual storage location and the new number.
3 . The method of claim 2 , further comprising:
calculating error detecting numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect; and
calculating correcting parity numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect.
4 . The method of claim 3 , further comprising:
calculating new error detecting numbers, wherein the calculating occurs after inserting the new number; and
calculating new correcting parity numbers, wherein the calculating occurs after inserting the new number.
5 . The method of claim 2 , further comprising:
calculating a difference between the incorrect number and the new number; and
adding the difference between the incorrect number and the new number to the error detecting numbers and the correcting parity numbers.
6 . The method of claim 2 , wherein the data block is a nine-number data block.
7 . The method of claim 1 , further comprising:
calculating error detecting numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect; and
calculating correcting parity numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect.
8 . The method of claim 7 , further comprising:
calculating new error detecting numbers, wherein the calculating occurs after inserting the new number; and
calculating new correcting parity numbers, wherein the calculating occurs after inserting the new number.
9 . The method of claim 1 , further comprising:
calculating a difference between the incorrect number and the new number; and
adding the difference between the incorrect number and the new number to the error detecting numbers and the correcting parity numbers.
10 . The method of claim 1 , wherein the data block is a nine-number data block.
11 . A cross point memory device having a data block arranged in a rectangular pattern, comprising:
means to determine that a number in an individual storage location is incorrect;
means to subtract the incorrect individual number from the from the data block; and
means to insert a new number into the data block from which the incorrect individual number has been removed.
12 . The cross point memory device of claim 11 , further comprising:
means to calculate a difference between the incorrect number in the individual storage location and the new number.
13 . The cross point memory device of claim 12 , further comprising:
means to calculate error detecting numbers; and
means to calculate correcting parity numbers.
14 . The cross point memory device of claim 13 , further comprising:
means to calculate new error detecting numbers; and
means to calculate new correcting parity numbers.
15 . The cross point memory device of claim 12 , further comprising:
means to calculating a difference between the incorrect number and the new number; and
means to add the difference between the incorrect number and the new number to the error detecting numbers and the correcting parity numbers.
16 . The cross point memory device of claim 15 , wherein the data block is a nine-number data block.
17 . The cross point memory device of claim 12 , wherein the data block is a nine-number data block.
18 . A memory storage device with increased speed comprising a cross point memory array having a plurality of memory cells arranged in columns and rows, the memory storage device comprising:
(i) means to target data bits of a subset of the plurality of memory cells in one of the columns;
(ii) means to determine error correcting values corresponding to new data bits to be written to the subset of the plurality of memory cells in the one of the columns;
(iii) means to write the new data bits to the subset of the plurality of memory cells in the one of the columns of the memory storage device; and
(iv) means to write error correcting bits corresponding to the error correcting values to the memory storage device;
wherein the plurality of memory cells in the one of the columns other than the subset are unchanged.
19 . The memory storage device of claim 18 , further comprising:
(i) means to remove an impact to the error detecting values of the data bits; and
(ii) means to incorporate an impact to the error detecting values of the new data bits.
20 . The memory storage device of claim 18 , further comprising:
(i) means to determine an impact to the error detecting values of the new data bits; and
(ii) means to update the error detecting values with the determination of the impact of the new data bits.