Controlling coupling in large cross-point memory arrays
View Patent ↗In various embodiments, quench switches are utilized within a cross-point memory array to minimize parasitic coupling in lines proximate selected lines.
1. A method of selecting a memory cell location within a cross-point memory array, the memory array comprising a plurality of wordlines intersecting a plurality of bitlines, each memory cell location being proximate a point of intersection between a wordline and a bitline, each wordline being electrically coupled to a driver device and a quench switch for minimizing parasitic coupling with adjacent wordlines, wherein the quench switch comprises a quench diode, the method comprising:
selecting a first wordline, the first wordline being disposed between a second wordline and a third wordline;
activating the quench switches coupled to the second wordline and the third wordline, thereby reducing parasitic coupling within the second and third wordlines resulting from selection of the first wordline; and
selecting the first bitline, thereby selecting the memory cell disposed at the point of intersection between the first wordline and the first bitline.
2. The method of claim 1 , wherein (i) selecting the first wordline comprises applying a first voltage thereto and (ii) activating the quench switches electrically coupled to the second and third wordlines comprises electrically connecting the second and third wordlines to a second voltage through the quench switches.
3. The method of claim 1 , wherein the first voltage is a positive voltage and the second voltage is a ground voltage.
4. The method of claim 1 , wherein at least one of the quench switches additionally comprises a transistor.
5. The method of claim 1 , wherein (i) the plurality of wordlines comprises a plurality of odd wordlines interleaved with a plurality of even wordlines, (ii) the quench switches of the odd wordlines are electrically connected together, and (iii) the quench switches of the even wordlines are electrically connected together.
6. The method of claim 1 , wherein (i) the plurality of wordlines comprises a plurality of odd wordlines interleaved with a plurality of even wordlines, (ii) a first plurality of odd wordlines comprises every other odd wordline, (iii) a second plurality of odd wordlines comprises the odd wordlines not within the first plurality of odd wordlines, (iv) a first plurality of even wordlines comprises every other even wordline, (v) a second plurality of even wordlines comprises the even wordlines not within the first plurality of even wordlines, (vi) the quench switches of the first plurality of odd wordlines are electrically connected together, (vii) the quench switches of the second plurality of odd wordlines are electrically connected together, (viii) the quench switches of the first plurality of even wordlines are electrically connected together, and (ix) the quench switches of the second plurality of even wordlines are electrically connected together.
7. The method of claim 6 , further comprising:
(a) if the first wordline is within the first plurality of odd wordlines, activating the quench switches electrically coupled to the second plurality of odd wordlines, thereby reducing parasitic coupling within the second plurality of odd wordlines resulting from selection of the first wordline;
(b) if the first wordline is within the second plurality of odd wordlines, activating the quench switches electrically coupled to the first plurality of odd wordlines, thereby reducing parasitic coupling within the first plurality of odd wordlines resulting from selection of the first wordline;
(c) if the first wordline is within the first plurality of even wordlines, activating the quench switches electrically coupled to the second plurality of even wordlines, thereby reducing parasitic coupling within the second plurality of even wordlines resulting from selection of the first wordline; and
(d) if the first wordline is within the second plurality of even wordlines, activating the quench switches electrically coupled to the first plurality of even wordlines, thereby reducing parasitic coupling within the first plurality of even wordlines resulting from selection of the first wordline.
8. The method of claim 7 , wherein (i) selecting the first wordline comprises applying a first voltage thereto, (ii) activating the quench switches electrically coupled to the second and third wordlines comprises electrically connecting the second and third wordlines to a second voltage through the quench switches, and (iii) activating the quench switches electrically coupled to the first plurality of odd wordlines, the second plurality of odd wordlines, the first plurality of even wordlines, or the second plurality of even wordlines comprises electrically connecting said wordlines to a third voltage through the quench switches.
9. The method of claim 8 , wherein (i) the second and third voltages are approximately equal and (ii) the first voltage is different from the second and third voltages.
10. A method of selecting a memory cell location within a cross-point memory array, the memory array comprising a plurality of wordlines intersecting a plurality of bitlines, each memory cell location being proximate a point of intersection between a wordline and a bitline, each wordline being electrically coupled to a driver device and a quench switch for minimizing parasitic coupling with adjacent wordlines, the method comprising:
selecting a first wordline, the first wordline being disposed between a second wordline and a third wordline;
activating the quench switches coupled to the second wordline and the third wordline, thereby reducing parasitic coupling within the second and third wordlines resulting from selection of the first wordline; and
selecting the first bitline, thereby selecting the memory cell disposed at the point of intersection between the first wordline and the first bitline wherein each wordline comprises a first end electrically connected to a first quench switch and a second end, opposite the first end, electrically connected to a second quench switch.
11. A memory device comprising:
a plurality of wordlines;
a plurality of bitlines intersecting the plurality of wordlines;
a plurality of memory cell locations each disposed proximate a point of intersection between a wordline and a bitline;
a plurality of quench switches, each quench switch being electrically connected to a wordline, wherein the quench switches comprise a quench diode; and
a plurality of driver devices, each driver device being electrically connected to a wordline,
wherein, when a wordline is selected, activation of the quench switches electrically connected to wordlines proximate the selected wordline reduces or substantially eliminates parasitic coupling within the wordlines proximate the selected wordline.
12. The memory device of claim 11 , wherein each quench switch additionally comprises a transistor.
13. The memory device of claim 11 , wherein (i) the plurality of wordlines comprises a plurality of odd wordlines interleaved with a plurality of even wordlines, (ii) the quench switches of the odd wordlines are electrically connected together, and (iii) the quench switches of the even wordlines are electrically connected together.
14. A memory device comprising:
a plurality of wordlines;
a plurality of bitlines intersecting the plurality of wordlines;
a plurality of memory cell locations each disposed proximate a point of intersection between a wordline and a bitline;
a plurality of quench switches, each quench switch being electrically connected to a wordline; and
a plurality of driver devices, each driver device being electrically connected to a wordline,
wherein, when a wordline is selected, activation of the quench switches electrically connected to wordlines proximate the selected wordline reduces or substantially eliminates parasitic coupling within the wordlines proximate the selected wordline, wherein each wordline comprises a first end electrically connected to a first quench switch and a second end, opposite the first end, electrically connected to a second quench switch.
15. The memory device of claim 11 , wherein (i) the plurality of wordlines comprises a plurality of odd wordlines interleaved with a plurality of even wordlines, (ii) a first plurality of odd wordlines comprises every other odd wordline, (iii) a second plurality of odd wordlines comprises the odd wordlines not within the first plurality of odd wordlines, (iv) a first plurality of even wordlines comprises every other wordline, (v) a second plurality of even wordlines comprises the even wordlines not within the first plurality of even wordlines, (vi) the quench switches of the first plurality of odd wordlines are electrically connected together, (vii) the quench switches of the second plurality of odd wordlines are electrically connected together, (viii) the quench switches of the first plurality of even wordlines are electrically connected together, and (ix) the quench switches of the second plurality of even wordlines are electrically connected together.