Method for forming PCM and RRAM 3-D memory cells
View Patent ↗A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.
1. A method of fabricating memory cells, comprising:
patterning and etching a metal to form a vertical post over a substrate and to form a plurality of holes;
depositing a second insulating layer within the plurality of holes;
etching the second insulating layer, wherein the etched second insulating layer has a top surface that is slanted; and
depositing a conductive material into the plurality of holes.
2. The method of claim 1 , wherein the metal is disposed over a first layer stack that comprises:
a first insulating layer;
a first memory layer;
a first conductor layer;
a second insulating layer;
a second memory layer; and
a second conductor layer.
3. The method of claim 2 , wherein the first layer stack further comprises: a first hard mask layer.
4. The method of claim 3 , wherein the first insulating layer is deposited onto a first side of a word line and a second side of the word line.
5. The method of claim 4 , wherein the first side of a word line is opposed to the second side of the word line.
6. The method of claim 5 , wherein the first side of a word line and the second side of a word line are facing the plurality of trenches.
7. The method of claim 1 , further comprising cantilevering the substrate during the etching of the second dielectric layer.
8. A memory device, comprising:
a substrate, wherein the substrate includes a plurality of selector contacts and wherein the selector contacts have an upper surface;
a first layer stack;
a first insulating layer;
a vertical post, wherein the vertical posts are disposed on the upper surface of the selector contacts;
means for angling a conductive material adjacent the vertical post; and
the conductive material.
9. The memory device of claim 8 , wherein the first layer stack comprises:
a first insulating layer;
a first memory layer;
a first conductor layer;
a second insulating layer;
a second memory layer; and
a second conductor layer.
10. The memory device of claim 9 , wherein the first layer stack further comprises: a hard mask layer.
11. The memory device of claim 10 , wherein the first insulating layer is disposed adjacent the vertical posts orthogonal to the second insulating layer.
12. The memory device of claim 8 , wherein the first insulating layer is disposed adjacent the vertical posts orthogonal to the second insulating layer.
13. The memory device of claim 8 , further comprising a hard mask layer over the vertical posts.
14. The memory device of claim 8 , wherein the vertical posts are Tungsten.
15. A method of fabricating a plurality of layers of memory cells comprising the steps of:
patterning and etching conductive post material to form a plurality of conductive posts that are separated by holes; and
filling the holes with sidewall liners;
cantilevering the sidewall liners;
etching the sidewall liners to form openings; and
depositing conductive materials in the openings to form a plurality of memory elements.
16. The method of claim 15 , further comprising the step of electrically connecting a conductive material in a hole with the conductive post material of a conductive post.
17. The method of claim 16 , wherein the cantilevering comprises preferentially etching one side of the sidewall liner over the opposite side of the sidewall liner.
18. The method of claim 15 , further comprising depositing a metal suitable for forming a Resistive RAM.
19. The method of claim 15 , further comprising depositing an oxide suitable for forming a Resistive RAM.
20. The method of claim 15 , further comprising depositing a Chalcogenide alloy suitable for forming a Phase-change memory cell.