4F2 SCR memory device
View Patent ↗A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F 2 . This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.
1. A memory device comprising an array of bipolar junction transistor devices whereby at least one of the gate connections to the bipolar junction devices is manufactured by growing silicon laterally in a trench;
a plurality of bit lines that are parallel to one another; and
a plurality of word lines that are parallel to one another, wherein each bit line is coupled to a plurality of information storage elements and each word line is coupled to the plurality of information storage elements wherein each information storage element is coupled to a respective input, a positive voltage supply and to ground.
2. The memory device of claim 1 further comprising one or more diode decoder arrays.
3. The memory device of claim 2 further comprising one or more schottky diodes.
4. The memory device of claim 1 further comprising having a plurality of CLSD devices in a two dimensional array whereby the bottom contacts are connected by the substrate.
5. The memory device of claim 1 further comprising having a plurality of CLSD devices in a two dimensional array whereby the top contacts, with an information storage element in series, are connected by a single top contact.
6. The memory device of claim 5 whereby the storage elements comprises at least one selected from the list of a phase-change material, a resistive ram material, a one-time-programmable material, a fuseable material, and an anti-fuseable material.
7. A memory array, comprising:
a plurality of threshold switching devices is constructed having an area per transistor of 2F 2 wherein the switching devices are bipolar junction transistors.
8. The memory array of claim 7 wherein a control input of the transistor is capacitively connected to one or two word lines.
9. The memory array of claim 8 , wherein and a gate control input is connected to one or two bit lines that are orthogonal to word lines.
10. The memory array of claim 7 , comprising:
a plurality of bit lines that are parallel to one another; and
a plurality of word lines that are parallel to one another, wherein the pluralities of bit lines are orthogonal to the plurality of word lines.
11. The memory array of claim 10 , wherein each bit line is coupled to a plurality of information storage elements.
12. The memory array of claim 11 , wherein each word line is coupled to a plurality of information storage elements.
13. The memory array of claim 12 , wherein each information storage element is coupled to a respective input.
14. The memory array of claim 13 , wherein each information storage element is additionally coupled to a positive voltage supply.
15. A memory array, comprising:
a plurality of bipolar junction transmitters is constructed having an area per transistor of 2F 2 a plurality of bit lines that are parallel to one another; and
a plurality of word lines that are parallel to one another, wherein the pluralities of bit lines are orthogonal to the plurality of word lines wherein each bit line is coupled to a plurality of information storage elements wherein each word line is coupled to a plurality of information storage elements wherein each information storage element is coupled to a respective input wherein each information storage element is additionally coupled to a positive voltage supply wherein each information storage element is additionally coupled to ground.
16. The memory array of claim 15 , wherein the plurality of information storage elements includes a first information storage element, a second information storage element, a third information storage element and a fourth information storage element, wherein the plurality of bit lines comprises a first bit line and a second bit line, and wherein the plurality of word lines comprises a first word line and a second word line.
17. The memory array of claim 16 , wherein the first bit line is coupled to the first information storage element and the second information storage element, wherein the first word line is coupled to the first information storage element and the third information storage element.
18. The memory array of claim 17 , wherein the second bit line is coupled to the third information storage element and the fourth information storage element and wherein the second word line is coupled to the second information storage element and the fourth information storage element.
19. The memory array of claim 18 , further comprising one or more schottky diodes.