IP Library Granted Patent US 11,152,425
Granted Patent B2
US 11,152,425 · App. 16/666,967 · Granted Oct 19, 2021

Cross-point spin-transfer torque magnetoresistive memory array and method of making the same

Inventors: Lei Wan (San Jose, CA); Jordan Katine (Mountain View, CA); Tsai-Wei Wu (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H01L27/224H01L43/02H01L43/12
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Quick Facts
Patent No.
US 11,152,425
App. No.
16/666,967
Granted
Oct 19, 2021
Kind
B2
Abstract

A memory device includes a cross-point array of spin-torque transfer MRAM cells. First rail structures laterally extend along a first horizontal direction. Each of the first rail structures includes a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer. Second rail structures laterally extend along a second horizontal direction. Each of the second rail structures includes a second electrically conductive line that overlies the first rail structures. A two-dimensional array of pillar structures is located between a respective one of the first rail structures and a respective one of the second rail structures. Each of the pillar structures includes a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction.

Claims (44)

1. A memory device including a two-dimensional array of spin-torque transfer MRAM cells, comprising:

first rail structures that laterally extend along a first horizontal direction and laterally spaced apart from each other, wherein each of the first rail structures comprises a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer;

second rail structures that laterally extend along a second horizontal direction that is different from the first horizontal direction and laterally spaced apart from each other, wherein each of the second rail structures comprises a second electrically conductive line that overlies the first rail structures; and

a two-dimensional array of pillar structures located between a respective one of the first rail structures and a respective one of the second rail structures, wherein each of the pillar structures comprises a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction of the reference layer,

wherein each of the first rail structures further comprises an antiferromagnetic layer or a synthetic antiferromagnetic structure including a vertical stack of a magnetic fixed layer, a coupling layer, and a respective one of the reference layers.

2. The memory device of claim 1 , further comprising a two-dimensional array of selectors located within the two-dimensional array of the pillar structures or within the second rail structures.

3. The memory device of claim 2 , wherein the two-dimensional array of selectors is located within the two-dimensional array of the pillar structures as a two-dimensional array of discrete selectors.

4. The memory device of claim 3 , wherein each of the pillar structures further comprises:

an electrically conductive capping layer located between a respective one of the free layers and a respective one of the selectors; and

an electrically conductive material layer located between the respective one of the selectors and a respective one of the second rail structures.

5. The memory device of claim 2 , wherein:

the two-dimensional array of selectors is located within the second rail structures and comprises portions of selector material rails that extend along the second horizontal direction; and

each of the selector material rails includes a respective column of selectors and contacts a respective underlying column of pillar structures within the two-dimensional array of pillar structures.

6. The memory device of claim 5 , wherein each of the pillar structures comprises

an electrically conductive capping layer located between a respective one of the free layers and a respective one of the selector material rails.

7. The memory device of claim 1 , wherein the two-dimensional array of pillar structures has a sidewall segment that not parallel to the first horizontal direction and is not parallel to the second horizontal direction.

8. The memory device of claim 1 , wherein each pillar structure within the two-dimensional array of pillar structures has a lateral extent along the second horizontal direction that is less than a width of a respective underlying one of the first rail structures along the second horizontal direction.

9. The memory device of claim 1 , wherein a pillar structure within the two-dimensional array of pillar structures has a sidewall segment that is parallel to the second horizontal direction and is laterally offset from sidewalls of a respective overlying one of the second rail structures along the first horizontal direction.

10. The memory device of claim 1 , wherein the pillar structures within the two-dimensional array of pillar structures have first sidewalls that are vertically coincident with sidewalls of the first rail structures.

11. The memory device of claim 10 , wherein the pillar structures within the two-dimensional array of pillar structures have second sidewalls that are vertically coincident with sidewalls of the second rail structures.

12. The memory device of claim 1 , wherein each of the first rail structures comprises a seed layer comprising at titanium, tantalum, platinum, or ruthenium, and located between a respective one of the first electrically conductive lines and a respective one of the synthetic antiferromagnetic structures or antiferromagnetic layers.

13. A memory device including a two-dimensional array of spin-torque transfer MRAM cells, comprising:

first rail structures that laterally extend along a first horizontal direction and laterally spaced apart from each other, wherein each of the first rail structures comprises a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer;

second rail structures that laterally extend along a second horizontal direction that is different from the first horizontal direction and laterally spaced apart from each other, wherein each of the second rail structures comprises a second electrically conductive line that overlies the first rail structures;

a two-dimensional array of pillar structures located between a respective one of the first rail structures and a respective one of the second rail structures, wherein each of the pillar structures comprises a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction of the reference layer;

a two-dimensional array of selectors located within the two-dimensional array of the pillar structures or within the second rail structures; and

a feature comprising:

(a) a first feature wherein the two-dimensional array of selectors is located within the two-dimensional array of the pillar structures as a two-dimensional array of discrete selectors; or

(b) a second feature wherein the two-dimensional array of selectors is located within the second rail structures and comprises portions of selector material rails that extend along the second horizontal direction, and each of the selector material rails includes a respective column of selectors and contacts a respective underlying column of pillar structures within the two-dimensional array of pillar structures.

14. The memory device of claim 13 , wherein the feature comprises the first feature.

15. The memory device of claim 13 , wherein the feature comprises the second feature.

16. A memory device including a two-dimensional array of spin-torque transfer MRAM cells, comprising:

first rail structures that laterally extend along a first horizontal direction and laterally spaced apart from each other, wherein each of the first rail structures comprises a vertical stack including, from bottom to top, a first electrically conductive line, a reference layer having a fixed magnetization direction, and a tunnel barrier layer;

second rail structures that laterally extend along a second horizontal direction that is different from the first horizontal direction and laterally spaced apart from each other, wherein each of the second rail structures comprises a second electrically conductive line that overlies the first rail structures;

a two-dimensional array of pillar structures located between a respective one of the first rail structures and a respective one of the second rail structures, wherein each of the pillar structures comprises a free layer having energetically stable magnetization orientations that are parallel or antiparallel to the fixed magnetization direction of the reference layer; and

at least one feature comprising:

(a) a first feature wherein the two-dimensional array of pillar structures has a sidewall segment that not parallel to the first horizontal direction and is not parallel to the second horizontal direction; or

(b) a second feature wherein each pillar structure within the two-dimensional array of pillar structures has a lateral extent along the second horizontal direction that is less than a width of a respective underlying one of the first rail structures along the second horizontal direction; or

(c) a third feature wherein a pillar structure within the two-dimensional array of pillar structures has a sidewall segment that is parallel to the second horizontal direction and is laterally offset from sidewalls of a respective overlying one of the second rail structures along the first horizontal direction; or

(d) a fourth feature wherein the pillar structures within the two-dimensional array of pillar structures have first sidewalls that are vertically coincident with sidewalls of the first rail structures.

17. The memory device of claim 16 , wherein the at least one feature comprises the first feature.

18. The memory device of claim 16 , wherein the at least one feature comprises the second feature.

19. The memory device of claim 16 , wherein the at least one feature comprises the third feature.

20. The memory device of claim 16 , wherein the at least one feature comprises the fourth feature.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 051717 FRAME 0716 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0385 →
SECURITY INTEREST Recorded Feb 4, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 051717/0716 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2019
From: WAN, LEI; KATINE, JORDAN; WU, TSAI-WEI
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 050864/0430 →
Cited By (1)
US 12,543,508