IP Library Granted Patent US 11,526,300
Granted Patent B2
US 11,526,300 · App. 17/236,730 · Granted Dec 13, 2022

Fast write on Merkle Tree for secure HMB

Inventors: Amir Segev (Meiter, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0656G06F3/0614G06F3/0623G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 11,526,300
App. No.
17/236,730
Granted
Dec 13, 2022
Kind
B2
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to set a decoder in data mode, read host memory buffer data and hashes from a host memory buffer, generate a first calculated hash, set the decoder in hash mode, generate a second calculated hash, and determine whether the second calculated hash is the same as a root hash. The controller is further configured to set an encoder in data mode, generate a first new hash, write new data and the first new hash to a host memory buffer, set the encoder to hash mode, calculate a second new hash, and update a root hash with the second new hash.

Claims (54)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

set a decoder in data mode;

read host memory buffer (HMB) data and hashes from an HMB;

send a trigger to an encoder indicating that the HMB data and the hashes from the HMB have been read, wherein a write flow of the encoder is delayed until receiving the trigger;

generate a first calculated hash;

set the decoder in hash mode;

generate a second calculated hash; and

determine whether the second calculated hash is the same as a root hash.

2. The data storage device of claim 1 , wherein while in the data mode, the decoder is configured to determine whether all data has been received from the HMB.

3. The data storage device of claim 1 , wherein while in the hash mode, the decoder is configured to determine whether all hashes have been received from the HMB.

4. The data storage device of claim 1 , the decoder is configured to determine whether the second calculated hash is a last hash.

5. The data storage device of claim 4 , wherein the controller is configured to indicate that a write operation has failed when the last hash is not the same as the root hash.

6. The data storage device of claim 1 , wherein the first calculated hash is generated after receiving all data read from the HMB.

7. The data storage device of claim 1 , wherein the second calculated hash is generated after receiving an entire hash from the HMB.

8. The data storage device of claim 1 , wherein the controller is further configured to:

set the encoder in data mode;

generate a first new hash with the encoder; and

determine whether all HMB data has arrived at the decoder.

9. The data storage device of claim 8 , wherein the controller is further configured to:

write new data and the first new hash to the HMB, wherein the writing occurs after determining that all HMB data has arrived at the decoder.

10. The data storage device of claim 9 , wherein the controller is further configured to:

calculate a second new hash; and

write the second new hash to the HMB.

11. The data storage device of claim 10 , wherein calculating the second new hash occurs after the decoder has generated the first calculated hash and the second calculated hash.

12. The data storage device of claim 11 , wherein the controller is configured to update the root hash with the second new hash after determining that the second calculated hash is the same as the root hash.

13. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

set an encoder in data mode;

generate a first new hash;

receive a trigger from a decoder, wherein the trigger indicates that host memory buffer (HMB) data and hashes from an HMB have been read by the decoder;

write new data and the first new hash to the, in response to receiving the trigger;

set the encoder to hash mode;

calculate a second new hash; and

update a root hash with the second new hash.

14. The data storage device of claim 13 , wherein the controller is further configured to determine whether all HMB data has arrived at the decoder prior to writing the new data and new hash to the HMB.

15. The data storage device of claim 13 , wherein the controller is further configured to calculate the second new hash after generating a second calculated hash at the decoder.

16. The data storage device of claim 13 , wherein the controller is further configured to determine whether the second new hash is the last hash.

17. The data storage device of claim 13 , wherein the controller is further configured to write the second new hash to HMB prior to updating the root hash.

18. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to:

generate a first calculated hash based upon data read from a host memory buffer (HMB);

generate a first trigger in response to generating the first calculated hash;

generate a second calculated hash based upon the first calculated hash and HMB hash read from the HMB;

generate a second trigger in response generating the second calculated hash:

prepare a new hash when both the first trigger and the second trigger are generated; and

compare the second calculated hash to a root hash to determine whether a write operation has failed.

19. The data storage device of claim 18 , wherein the controller is further configured to:

write data associated with the new hash and the new hash to HMB; and

write the new hash to the root hash upon determining the second calculated hash is equal to the root hash.

20. The data storage device of claim 19 , wherein the generating a first calculated hash, generating a second calculated hash, and comparing is performed by a decoder, and wherein preparing, writing data, and writing the new hash is performed by an encoder.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2021
From: SEGEV, AMIR; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056040/0712 →
Cited By (1)
US 12,499,010