IP Library Granted Patent US 11,532,592
Granted Patent B2
US 11,532,592 · App. 16/870,176 · Granted Dec 20, 2022

Capacitor die for stacked integrated circuits

Inventors: David C. Zhang (Milpitas, CA); Pranav Balachander (Santa Clara, CA)
Assignee: Western Digital Technologies, Inc.
H01L24/49H01L23/5226H01L23/5383H01L23/66H05K1/0243H01L2224/49174
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Quick Facts
Patent No.
US 11,532,592
App. No.
16/870,176
Granted
Dec 20, 2022
Kind
B2
Abstract

An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.

Claims (31)

1. An apparatus comprising:

a die stack comprising a first die and a second die disposed above a substrate; and

a capacitor die disposed in the die stack between the first die and the second die, wherein:

the capacitor die comprises a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die;

the capacitor die further comprises a plurality of switches coupled to the plurality of integrated circuit capacitors; and

the plurality of switches are selectively configured to form the desired capacitor value.

2. The apparatus of claim 1 , wherein the capacitor die further comprises a plurality of bond pads coupled to the integrated circuit capacitors, each bond pad sized to accommodate multiple wire bonds.

3. The apparatus of claim 1 , wherein the capacitor die further comprises a first plurality of bond pads coupled to a first capacitor plate of the integrated circuit capacitors, and a second plurality of bond pads coupled to a second capacitor plate of the integrated circuit capacitors.

4. The apparatus of claim 1 , wherein the capacitor die further comprises a plurality of bond pads coupled to the integrated circuit capacitors, and wherein the apparatus further comprises a plurality of wire bonds coupled to the bond pads.

5. The apparatus of claim 1 , wherein the first die comprises power supply bond pads coupled to the capacitor die.

6. The apparatus of claim 1 , wherein the substrate comprises power supply contact pads coupled to the capacitor die.

7. The apparatus of claim 1 , wherein the substrate comprises a first power supply contact pad coupled by way of a first plurality of wire bonds to a first bond pad of the capacitor die, and a second power supply contact pad coupled by way of a second plurality of wire bonds to a second bond pad of the capacitor die.

8. The apparatus of claim 1 , wherein the capacitor die comprises a power supply bypass capacitor.

9. The apparatus of claim 1 , wherein the capacitor die comprises dimensions the same as dimensions of the first die and the second die.

10. The apparatus of claim 1 , wherein the capacitor die comprises a first set of first bond pads and a first set of second bond pads disposed adjacent a first side of the capacitor die, and a second set of first bond pads and a second set of second bond pads disposed adjacent a second side of the capacitor die.

11. An apparatus comprising:

a die stack comprising a plurality of die disposed above a substrate; and

a capacitor die disposed in the die stack and comprising a plurality of integrated circuit capacitors each comprising a first capacitor plate coupled to a first bond pad and a second capacitor plate coupled via a corresponding one of a plurality of switches to a second bond pad,

wherein the first and second bond pads are configured to accommodate multiple wire bonds.

12. The apparatus of claim 11 , wherein the plurality of switches are configured to selectively couple the integrated circuit capacitors to form a desired capacitor value.

13. The apparatus of claim 11 , wherein:

the die stack comprises a die comprising power supply bond pads coupled to the capacitor die bond pads with a first plurality of wire bonds; and

the substrate comprises power supply contact pads coupled to the capacitor die bond pads with a second plurality of wire bonds.

14. The apparatus of claim 11 , wherein the capacitor die further comprises a resistor configured for terminating signals.

15. A method comprising:

disposing a capacitor die in a die stack above a substrate, the capacitor die comprising a plurality of integrated circuit capacitors coupled to bond pads that are configured to accommodate multiple wire bonds, the substrate comprising power supply contact pads;

selectively coupling the plurality of integrated circuit capacitors to tune a capacitor value of the capacitor die; and

selectively coupling the bond pads to the power supply contact pads via a plurality of wire bonds to tune an inductance of the wire bonds.

16. The method of claim 15 , further comprising selectively tuning the capacitor value of the capacitor die and the inductance of the wire bonds to reduce power supply noise at a die in the die stack.

17. The method of claim 15 , further comprising selectively tuning the capacitor value of the capacitor die and the inductance of the wire bonds to create a low impedance profile in a target frequency range of a power delivery network comprising the power supply contact pads.

18. The method of claim 15 , further comprising electrically coupling the bond pads of the capacitor die to power supply bond pads of a die in the die stack.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2020
From: ZHANG, DAVID C.; BALACHANDER, PRANAV
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052613/0852 →