IP Library Granted Patent US 11,169,584
Granted Patent B2
US 11,169,584 · App. 16/836,424 · Granted Nov 9, 2021

Dual-connector storage system and method for simultaneously providing power and memory access to a computing device

Inventors: Eldhose Peter (Bengaluru, IN); Akhilesh Yadav (Bengaluru, IN); Rakesh Balakrishnan (Bengaluru, IN)
Assignee: Western Digital Technologies, Inc.
G06F1/266G11C7/10H01R13/6675G06F2213/0042
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Quick Facts
Patent No.
US 11,169,584
App. No.
16/836,424
Granted
Nov 9, 2021
Kind
B2
Abstract

A dual-connector storage system and method for simultaneously providing power and memory access to a computing device are provided. In one embodiment, the storage system comprises a memory, a first connector, a second connector, and a controller. The controller is configured to provide power received from the second connector to a computing device connected with the first connector while also allowing the computing device to access the memory via the first connector. Other embodiments are provided.

Claims (40)

1. A storage system, comprising:

a memory;

a first connector;

a second connector; and

a controller configured to:

represent the storage system as a host to a computing device connected to the first connector; then

provide power received from the second connector to the computing device via the first connector; then

instruct the computing device to take over as the host, wherein power is still provided to the computing device via the first connector after the computing device takes over as the host; and then

allow the computing device to access the memory via the first connector while still providing the computing device with power via the first connector.

2. The storage system of claim 1 , wherein the first connector is a micro universal serial bus connector, and wherein the controller is further configured to represent the storage system as the host to the computing device by grounding an identification (ID) pin of the first connector.

3. The storage system of claim 1 , wherein the first connector is a Type-C universal serial bus connector, and wherein the controller is further configured to represent the storage system as the host to the computing device by switching channel configuration (CC) pins of the first connector to high through a pull-up resistor (Rp).

4. The storage system of claim 1 , wherein the computing device takes over as the host using a host negotiation protocol.

5. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

6. The storage system of claim 1 , wherein the first connector is configured to be removably connected with the computing device, and wherein the second connector is configured to be removable connected with a power source.

7. The storage system of claim 1 , wherein one of the first connector and the second connector is a universal serial bus connector, and wherein the other of the first connector and the second connector is a micro universal serial bus connector.

8. A method comprising:

performing the following in a storage system comprising a memory, a first connector, and a second connector:

instructing a computing device connected to the storage system via the first connector that the storage system is a host; then

providing power received via the second connector to the computing device via the first connector; then

instructing the computing device to take over as the host, wherein power is still provided to the computing device via the first connector after the computing device takes over as the host; and then

allowing the computing device to access the memory via the first connector while still providing the computing device with power via the first connector.

9. The method of claim 8 , wherein the first connector is a micro universal serial bus connector, and wherein the storage system instructs the computing device that the storage system is the host by grounding an identification (ID) pin of the first connector.

10. The method of claim 8 , wherein the first connector is a Type-C universal serial bus connector, and wherein the storage system instructs the computing device that the storage system is the host by switching channel configuration (CC) pins of the first connector to high through a pull-up resistor (Rp).

11. The method of claim 8 , wherein the computing device takes over as the host using a host negotiation protocol.

12. The method of claim 8 , wherein the memory comprises a three-dimensional memory.

13. The method of claim 8 , wherein the first connector is configured to be removably connected with the computing device, and wherein the second connector is configured to be removable connected with a power source.

14. A storage system, comprising:

a memory;

a first connector;

a second connector;

means for representing the storage system as a host to a computing device connected to the first connector;

means for providing power received from the second connector to the computing device via the first connector;

means for instructing the computing device to take over as the host, wherein power is still provided to the computing device via the first connector after the computing device takes over as the host; and

means for allowing the computing device to access the memory via the first connector while still providing the computing device with power via the first connector.

15. The storage system of claim 1 , wherein the first and second connectors are the only connectors of the storage system.

16. The method of claim 8 , wherein the first and second connectors are the only connectors of the storage system.

17. The storage system of claim 14 , wherein the first and second connectors are the only connectors of the storage system.

18. The storage system of claim 1 , wherein the first and second connectors are both male connectors and are positioned on opposite ends of the storage system.

19. The method of claim 8 , wherein the first and second connectors are both male connectors and are positioned on opposite ends of the storage system.

20. The storage system of claim 14 , wherein the first and second connectors are both male connectors and are positioned on opposite ends of the storage system.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: PETER, ELDHOSE; YADAV, AKHILESH; BALAKRISHNAN, RAKESH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052277/0116 →
Cited By (1)
US 12,710,869