Granted Patent B1

US 9,948,322 · App. 14/698,766 · Granted Apr 17, 2018

Abstract

Claims (42)

1. A circuit, comprising:

a merge multiplexer;

first and second multiplexers, wherein the first multiplexer is configured to output sectors of a second data frame to the second multiplexer and the merge multiplexer;

third and fourth multiplexers, wherein the third multiplexer is configured to output sectors of a first data frame to the fourth multiplexer and the merge multiplexer; and

a logic device configured to:

input sectors of the first data frame and the second data frame that are output from the fourth multiplexer and the second multiplexer, respectively; and

perform an error check on a first check-data frame comprising the sectors corresponding to sectors in the first data frame and a second check-data frame comprising the sectors corresponding to sectors in the second data frame;

wherein the merge multiplexer is configured to merge one or more sectors from the first multiplexer with one or more sectors from the second multiplexer based on a merge mask to form a merged output data frame,

wherein at least some of the sectors in the first and second check-data frames are transmitted on a subset of a plurality of data paths different from a subset of the plurality of data paths that transmits sectors of the merged output data frame, and

wherein the error check verifies the merged output data frame.

2. The circuit of claim 1 , further comprising:

an output multiplexer configured to:

input sectors of the merged output data frame that are output from the merge multiplexer;

output the sectors of the merged output data frame to the second multiplexer if the sectors of the merged output data frame were selected at the merge multiplexer from the second data frame; and

output the sectors of the merged output data frame to the fourth multiplexer if the sectors of the merged output data frame were selected at the merge multiplexer from the first data frame.

3. The circuit of claim 2 , wherein the output multiplexer is further configured to output the sectors of the merged output data frame on at least a portion of the plurality of data paths that transmits the sectors of the merged output data frame to the logic device.

4. The circuit of claim 1 , wherein the merge mask indicates the sectors of the first and second data frames to be merged into the output data frame.

5. The circuit of claim 1 , wherein the logic device is further configured to reconstruct the first check-data frame and the second check-data frame with their respective sectors that correspond to the first and second data frames after the sectors that correspond to the first and second data frames are transmitted through selected ones of the multiplexers.

6. The circuit of claim 1 , wherein the logic device is further configured to:

calculate an error check code for at least one of the first check-data frame and the second check-data frame; and

compare the calculated error check code with an error check code for the at least one of the first data frame and the second data frame, respectively.

7. The circuit of claim 6 , wherein the calculated error check codes and the error check codes for the first data frame and the second data frame comprise cyclic redundancy codes.

8. A data storage device comprising the circuit of claim 1 .

9. A method, comprising:

outputting sectors of a second data frame from a first multiplexer to a second multiplexer and a merge multiplexer;

outputting sectors of a first data frame from a third multiplexer to a fourth multiplexer and the merge multiplexer;

inputting sectors of the first data frame and the second data frame that are output from the fourth multiplexer and the second multiplexer, respectively, to a logic device;

performing, by the logic device, an error check on a first check-data frame comprising the sectors corresponding to sectors in the first data frame and a second check-data frame comprising sectors corresponding to sectors in the second data frame; and

merging, by the merge multiplexer, one or more sectors from the first multiplexer with one or more sectors from the second multiplexer based on a merge mask to form a merged output data frame,

wherein at least some of the sectors in the first and second check-data frames are transmitted on a subset of a plurality of data paths different from a subset of the plurality of data paths that transmits sectors of the merged output data frame, and

wherein the error check verifies the merged output data frame.

10. The method of claim 9 , further comprising:

inputting to an output multiplexer sectors of the merged output data frame that are output from the merge multiplexer;

outputting from the output multiplexer the sectors of the merged output data frame to the second multiplexer if the sectors of the merged output data frame were selected at the merge multiplexer from the second data frame; and

outputting from the output multiplexer the sectors of the merged output data frame to the fourth multiplexer if the sectors of the merged output data frame were selected at the merge multiplexer from the first data frame.

11. The method of claim 10 , further comprising outputting by the output multiplexer the sectors of the merged output data frame on at least a portion of the plurality of data paths that transmits the sectors of the merged output data frame to the logic device.

12. The method of claim 9 , wherein the merge mask indicates the sectors of the first and second data frames to be merged into the output data frame.

13. The method of claim 9 , further comprising reconstructing by the logic device the first check-data frame and the second check-data frame with their respective sectors that correspond to the first and second data frames after the sectors that correspond to the first and second data frames are transmitted through selected ones of the multiplexers.

14. The method of claim 9 , further comprising:

calculating by the logic device an error check code for at least one of the first check-data frame and the second check-data frame; and

comparing by the logic device the calculated error check code with an error check code for the at least one of the first data frame and the second data frame, respectively.

15. The method of claim 14 , wherein the calculated error check codes and the error check codes for the first data frame and the second data frame comprise cyclic redundancy codes.

Assignments (16)