Implementing deposition growth method for magnetic memory
View Patent ↗A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.
1. A method for implementing a magnetic memory array comprising:
forming a plurality of magnetic pillar memory cells includes a first conductor M 1 being formed of a magnetic material, and a second conductor M 2 being more electrically conductive than said conductor M 1 including:
growing said second conductor M 2 ;
coating said second conductor M 2 with a non-magnetic spacer layer;
growing said first magnetic conductor M 1 over said coated second conductor M 2 ;
depositing an oxide barrier over said grown first magnetic conductor M 1 forming magnetic pillar memory cells; and
depositing an interlayer dielectric (IDL) stack of word planes separated by a respective IDL on the first magnetic conductor M 1 , wherein the word planes have a magnetization state anti-parallel to a magnetization state of the second conductor M 2 ; wherein the first conductor M 1 is programmable to a parallel and anti-parallel magnetization state.
2. The method as recited in claim 1 wherein growing said second conductor M 2 includes forming said second conductor M 2 of a magnetic material.
3. The method as recited in claim 1 wherein growing said second conductor M 2 includes forming said second conductor M 2 of a non-magnetic material.
4. The method are recited in claim 1 includes sharing a bit line only by said magnetic pillar memory cells inside said respective pillar holes.
5. The method as recited in claim 1 wherein forming said magnetic pillar memory cells includes providing a complementary metal oxide semiconductor (CMOS) wafer having a CMOS defined pad pattern, and growing said magnetic pillar memory cells on said CMOS defined pad pattern.
6. The method as recited in claim 5 includes treating said CMOS defined pad pattern for providing a source of growth for said plurality of magnetic pillar memory cells.
7. The method as recited in claim 1 including forming vias in said IDL stack, and forming other conductive electrical connections.
8. The method as recited in claim 1 wherein growing said second conductor M 2 and growing said first conductor M 1 includes each said first conductor M 1 and said second conductor M 2 not being patterned.
9. A method for implementing a magnetic memory array comprising:
forming a plurality of magnetic pillar memory cells includes a first conductor M 1 being formed of a magnetic material, and a second conductor M 2 being more electrically conductive than said conductor M 1 including:
growing said second conductor M 2 ;
coating said second conductor M 2 with a non-magnetic spacer layer;
growing said first magnetic conductor M 1 over said coated second conductor M 2 ;
depositing an oxide barrier over said grown first magnetic conductor M 1 forming magnetic pillar memory cells; and
depositing an interlayer dielectric (IDL) stack of word planes separated by a respective IDL wherein growing said first conductor M 1 includes forming said first conductor M 1 of said magnetic material having a metallic granularity enabling independent programming of each said magnetic pillar memory cell.
10. A method for implementing a magnetic memory array comprising:
forming a plurality of magnetic pillar memory cells includes a first conductor M 1 being formed of a magnetic material, and a second conductor M 2 being more electrically conductive than said conductor M 1 including:
growing said second conductor M 2 ;
coating said second conductor M 2 with a non-magnetic spacer layer;
growing said first magnetic conductor M 1 over said coated second conductor M 2 ;
depositing an oxide barrier over said grown first magnetic conductor M 1 forming magnetic pillar memory cells; and
depositing an interlayer dielectric (IDL) stack of word planes separated by a respective IDL includes sharing each said respective word plane by all magnetic pillar memory cells in a respective plane level.