IP Library › Granted Patent US 12,229,423
Granted Patent B2
US 12,229,423 · App. 18/348,314 · Granted Feb 18, 2025

Read collision avoidance in sequential mixed workloads

Inventors: Neil Hutchison (Hudsonville, MI); Haining Liu (Irvine, CA); Jerry Lo (Walnut, CA); Sergey Anatolievich Gorobets (Edinburgh, GB)
Assignee: Sandisk Technologies, Inc.
G06F3/0635G06F3/061G06F3/0658G06F3/0679
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Quick Facts
Patent No.
US 12,229,423
App. No.
18/348,314
Granted
Feb 18, 2025
Kind
B2
Abstract

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

Claims (50)

1. A data storage device, comprising:

a non-volatile memory comprising a plurality of memory dies; and

a controller configured to control the non-volatile memory and communicate with a host, wherein the controller is configured to:

receive a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;

write a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and

read the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern, wherein:

the sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies; and

the sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and wherein:

the first order associated with the sequential write pattern is a random order, and the second order associated with the sequential read pattern is a sequential order; or

the controller is configured to, based on one or more future read operations, reorder the first order associated with the sequential write pattern to avoid writing to any memory dies of the plurality of memory dies while they are being read.

2. The data storage device of claim 1 , wherein the controller is further configured to, while writing the first data stripe associated with the first superblock to the plurality of memory dies, read a previously written data stripe associated with a previously written superblock of the plurality of superblocks from the plurality of memory dies.

3. The data storage device of claim 2 , wherein the controller is configured to read the previously written data stripe using the sequential read pattern.

4. The data storage device of claim 1 , wherein differences in the first order and the second order cause the controller to avoid simultaneously writing to and reading from a same memory die of the plurality of memory dies.

5. The data storage device of claim 1 , wherein:

the plurality of memory dies includes a total of N memory dies, N being an integer greater than or equal to 2; and

differences in the first order and the second order cause the controller to simultaneously write to and read from a same memory die of the plurality of memory dies fewer than N/2 times while a given data stripe is being written.

6. The data storage device of claim 1 , wherein:

the mixed workload is characterized by 50% write commands and 50% read commands; and

each write command included in the mixed workload corresponds to a respective read command included in the mixed workload.

7. The data storage device of claim 1 , wherein the controller is configured to:

detect the one or more future read operations using a sequential read ahead algorithm.

8. The data storage device of claim 7 , wherein the controller is configured to reorder the first order based on a degree of freedom associated with the first order for a given data stripe.

9. A method of operating a data storage device, the method comprising:

at a data storage device including a non-volatile memory comprising a plurality of memory dies, and a controller configured to control the non-volatile memory and communicate with a host:

receiving a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;

writing a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and

reading the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern,

wherein:

the sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies; and

the sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and

wherein:

the first order associated with the sequential write pattern alternates between:

a first sequential order having a first sequence of memory dies; and

a second sequential order having a second sequence of memory dies opposite the first sequence of memory dies; and

the second order associated with the sequential read pattern is a sequential order having the first sequence of memory dies.

10. The method of claim 9 , wherein:

the mixed workload is characterized by 50% write commands and 50% read commands; and

each write command included in the mixed workload corresponds to a respective read command included in the mixed workload.

11. A data storage device, comprising:

a non-volatile memory comprising a plurality of memory dies; and

a controller configured to control the non-volatile memory and communicate with a host, wherein the controller includes:

means for receiving a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;

means for writing a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and

means for reading the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern, and

wherein:

the sequential write pattern causes the means for writing to write to the plurality of memory dies in a first order of memory dies; and

the sequential read pattern causes the means for reading to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and

wherein:

the first order associated with the sequential write pattern is a sequential order that begins with a random memory die of the plurality of memory dies for each successive data stripe being written, or that begins with a memory die being identified as a last memory die used to read prior to writing a given data stripe; and

the second order associated with the sequential read pattern is a sequential order that begins with a same memory die of the plurality of memory dies for each successive data stripe being read.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2023
From: HUTCHISON, NEIL; LIU, HAINING; LO, JERRY; GOROBETS, SERGEY ANATOLIEVICH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064233/0219 →
Continuity (2)
Provisional Application 63413128 · Oct 4, 2022
Related Publication 20240118821A1 · Apr 11, 2024
References Cited (15)
US 9021192B1 · Kang et al. · 2015 [cited by applicant]
US 9218283B2 · Gorobets et al. · 2015 [cited by applicant]
US 9508437B2 · Parker et al. · 2016 [cited by applicant]
US 9652379B1 · Syu et al. · 2017 [cited by applicant]
US 10528464B2 · Ishiyama et al. · 2020 [cited by applicant]
US 10922014B1 · Henze · 2021 [cited by applicant]
US 11593262B1 · Henze · 2023 [cited by examiner]
US 20040215912A1 · Vergis · 2004 [cited by examiner]
US 20120084484A1 · Post · 2012 [cited by examiner]
US 20130250677A1 · Nam et al. · 2013 [cited by applicant]
US 20180173460A1 · Bandic et al. · 2018 [cited by applicant]
US 20210279170A1 · Liu et al. · 2021 [cited by applicant]
US 20210373812A1 · Subbarao · 2021 [cited by applicant]
US 20220083463A1 · Muchherla et al. · 2022 [cited by applicant]
US 20240062823A1 · Zhou · 2024 [cited by examiner]