IP Library Granted Patent US 11,003,387
Granted Patent B2
US 11,003,387 · App. 16/053,695 · Granted May 11, 2021

Combined data and control for multi-die flash

Inventors: Yoav Markus (Tel-Aviv, IL); Alexander Bazarsky (Holon, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0604G06F3/0679G06F13/1642G06F13/1668G06F13/4282
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Quick Facts
Patent No.
US 11,003,387
App. No.
16/053,695
Granted
May 11, 2021
Kind
B2
Abstract

An arrangement for providing a combined data and control signal for a multi die flash, comprising, a memory arrangement, the memory arrangement comprising at least two dies, a controller configured to send and receive signals to the memory arrangement and a common line connected to the memory arrangement and the controller and configured to transmit the signals from the controller to the at least two dies, wherein the arrangement is configured to provide a combined data and combined control signals to the multi-die flash.

Claims (71)

1. An arrangement for providing a combined data and control signal for a multi die memory, comprising:

a memory arrangement, the memory arrangement comprising at least two dies, each die of the at least two dies configured to receive a combined data and control signal comprising a plurality of signals, each of the plurality of signals being at a different voltage corresponding to one die of the at least two dies, the combined data and control signal comprising one or more of data signals or control signals;

a controller configured to send and receive the combined data and control signal comprising the plurality of signals, to and from the memory arrangement; and

a common line connected to the memory arrangement and the controller, configured to transmit the combined data and control signal from the controller to the at least two dies, wherein the arrangement is configured to provide the combined data and control signal to each respective one of the at least two dies in the multi die memory based on the voltage of each of the plurality of signals.

2. The arrangement according to claim 1 , wherein there are four dies.

3. The arrangement according to claim 1 , further comprising:

a digital to analog converter configured between the memory arrangement and the controller; and

an analog to digital converter for each of the at least two dies.

4. The arrangement according to claim 1 , further comprising:

an analog to digital converter configured in the controller; and

a digital to analog converter in each of the at least two dies.

5. The arrangement according to claim 1 , wherein the controller further comprises:

a clock synchronization arrangement configured to synchronize the signals transmitted from the controller to a clock signal.

6. The arrangement according to claim 1 , wherein the controller further comprises:

a direction synchronization arrangement configured to specify a direction upon which the signals may travel on the common line.

7. The arrangement according to claim 1 , wherein the memory is a flash memory.

8. The arrangement according to claim 7 , wherein the flash memory is a NAND flash memory.

9. The arrangement according to claim 3 , further comprising:

a resistor connected to ground between the digital to analog converter and the analog to digital converter.

10. A method to operate a multi-die flash, comprising:

receiving data in a memory arrangement at a controller for the multi-die flash, wherein the data includes a request to perform a command at the memory arrangement;

generating a command at the controller to perform at the multi-die flash, wherein separate command and separate data for at least two dies are combined in the generated command;

transmitting the command from the controller to the at least two dies of the memory arrangement over a single line at several voltage levels, each one of the several voltage levels corresponding to one die of the at least two dies;

receiving the command at the at least two dies and discerning between the separate command and separate data for each of the at least two dies based on voltage levels; and

performing the command at the at least two dies of the memory arrangement.

11. The method according to claim 10 , wherein the memory arrangement is a flash memory.

12. The method according to claim 11 , wherein the flash memory is a NAND flash memory.

13. The method according to claim 10 , further comprising:

performing a digital to analog conversion of the transmitted command and data from the controller to at least one die of the memory arrangement over a single line.

14. The method according to claim 13 , further comprising:

performing an analog to digital conversion of the command and the data at the at least one die when received.

15. The method according to claim 10 , wherein the performing the command at the at least two dies of the memory arrangement is a write command.

16. A memory arrangement, comprising:

means for receiving data from a host at a controller for a multi-die flash;

means for generating a command at the controller to perform at the multi-die flash;

means for transmitting the command and data from the controller to at least two die of the memory arrangement over a single line at two voltage levels, each of the two voltage levels corresponding to one of the at least two die of the memory arrangement;

means for discerning the voltage from the at least two voltage levels and receiving the command and data at each of the at least two die; and

means for performing the command at the at least two die of the memory arrangement.

17. The memory arrangement according to claim 16 , further comprising:

means for performing a digital to analog conversion of the transmitting the command and data from the controller to at least one die of the memory arrangement over the single line.

18. The memory arrangement according to claim 17 , further comprising:

means for performing an analog to digital conversion of the command and the data at the at least one die when received.

19. A method to perform a command and simultaneously send data to a multi-die solid state drive, comprising:

receiving data including a request at a controller within the multi-die solid state drive;

generating a command at the controller to perform at the multi-die solid state drive;

transmitting the command and data from the controller at least two different voltage levels on a signal comprising multiple voltages, over a single line, to at least two die of the solid state drive;

receiving the command from the controller and the data at the at least two die and discerning one of the at least two different voltage levels from the multiple voltages at each of the at least two die; and

performing the command at the at least two die of the solid state drive.

20. The method according to claim 19 , wherein the solid state drive includes NAND flash memory.

21. The method according to claim 19 , further comprising:

performing a digital to analog conversion of the transmitting the command and data from the controller to at least two die of the solid state drive.

22. The method according to claim 21 , further comprising:

performing an analog to digital conversion of the transmitting the command and data from the controller to the at least two die of the solid state drive when received.

23. The method according to claim 19 , wherein the performing the command at the at least two die of the solid state drive is a write command.

24. An arrangement to transmit a command and send data simultaneously perform to a multi-die memory arrangement, comprising:

means for receiving the data and a request from a host at a controller connected to the multi-die memory arrangement;

means for generating a command at the controller to perform at the multi-die memory arrangement;

means for transmitting the command and data from the controller at a voltage on a signal comprising multiple voltages, each voltage of the multiple voltages corresponding to one die of the multi-die memory arrangement; wherein the transmitting occurs over a single connection between the controller and the at least one die; and

means for discerning the voltage from the multiple voltages and receiving the command from the controller and the data at the at least one die.

25. The arrangement according to claim 24 , further comprising:

means for performing a digital to analog conversion of the transmitting the command and data from the controller to at least one die of the memory arrangement.

26. The arrangement according to claim 24 , further comprising:

means for performing an analog to digital conversion of the transmitting the command and data from the controller to at least one die of the memory arrangement when received.

27. A method to perform a command and simultaneously send data to a multi-die flash memory arrangement, comprising:

receiving the data including a request at a controller connected to the multi-die flash memory arrangement;

generating a command at the controller to perform at the multi-die flash memory arrangement;

determining a direction of transmission of data over a single line connected to the controller and the multi-die flash memory arrangement;

determining when to transmit the command and data from a controller according to a clock synchronization arrangement;

determining a voltage at which to transmit the command and data from the controller, as part of a multi-voltage signal;

transmitting the command and data from the controller to at least two die of the flash memory arrangement at a time determined by the clock synchronization arrangement wherein the voltage is discernable by one of the at least two die, wherein the transmitting occurs over a common line a single connection between the controller and the at least two die and the transmitting includes a combined control portion and a combined data portion;

receiving the command from the controller and the data at the at least two die; and performing the command at the at least two die of the flash memory arrangement.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2018
From: MARKUS, YOAV; BAZARSKY, ALEXANDER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046826/0932 →
Continuity (2)
Continuation In Part 15824658 · Nov 28, 2017
Related Publication 20190163397A1 · May 30, 2019