Data storage system for improving data throughput and decode capabilities
Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.
1. A data storage system, comprising:
a plurality of memory devices; and
one or more controllers configured to cause:
converting data into a codeword having different portions; and
transferring the different portions of the codeword to different memory devices among the plurality of memory devices, to store the different portions of the codeword at a first address in the different memory devices,
wherein the first address is a same address in the different memory devices.
2. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: obtaining the first address to store the different portions of the codeword, prior to the transferring.
3. The data storage system of claim 1 , wherein the plurality of memory devices are a plurality of physical non-volatile memory components.
4. The data storage system of claim 1 , wherein transferring the different portions of the codeword to the different memory devices comprises transferring, in parallel, the different portions of the codeword to the different memory devices.
5. The data storage system of claim 1 , wherein the one or more controllers is configured to transfer the different portions of the codeword to the different memory devices by transferring, in parallel, a first portion of the codeword among the different portions of the codeword to a first memory device via a first set of a plurality of input/output lines of a bus at the first address in the first memory device and a second portion of the codeword among the different portions of the codeword to a second memory device via a second set of the plurality of input/output lines of the bus at the first address in the second memory device.
6. The data storage system of claim 1 , wherein the one or more controllers are configured to cause:
reading, in parallel, the different portions of the codeword from the different memory devices among the plurality of memory devices; and
decoding the codeword comprising the different portions of the codeword.
7. The data storage system of claim 1 , wherein a bit error rate of at least one of the plurality of memory devices is higher than a bit error rate of other memory devices of the plurality of memory devices, and wherein the data storage system is configured to spread the codeword over the plurality of memory devices to reduce a sensitivity of a decoder to a physical defect in one of the plurality of memory devices.
8. The data storage system of claim 7 , wherein the other memory devices are configured to compensate for the higher bit error rate of the at least one of the plurality of memory devices.
9. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: communicating a first control signal to a first memory device among the plurality of memory devices and to a second memory device among the plurality of memory devices, via a first set of a plurality of input/output lines coupling the one or more controllers to the first memory device and the second memory device.
10. The data storage system of claim 9 , wherein the one or more controllers are configured to cause: communicating, in parallel, (i) a second control signal to the first memory device via a second set of the plurality of input/output lines, and (ii) a third control signal to the second memory device via a third set of the plurality of input/output lines, wherein the third set of the plurality of input/output lines is coupled to the one or more controllers and the second memory device.
11. A method, comprising:
converting data into a codeword having different portions; and
transferring the different portions of the codeword to different memory devices among a plurality of memory devices, to store the different portions of the codeword at a first address in the different memory devices,
wherein the first address is a same address in the different memory devices.
12. The method of claim 11 , comprising obtaining the first address to store the different portions of the codeword, prior to the transferring.
13. The method of claim 11 , wherein transferring the different portions of the codeword to the different memory devices comprises transferring, in parallel, the different portions of the codeword to the different memory devices.
14. The method of claim 11 , wherein the transferring comprises transferring, in parallel, a first portion of the codeword among the different portions of the codeword to a first memory device via a first set of a plurality of input/output lines of a bus at the first address in the first memory device and a second portion of the codeword among the different portions of the codeword to a second memory device via a second set of the plurality of input/output lines of the bus at the first address in the second memory device.
15. The method of claim 11 , wherein a bit error rate of at least one of the plurality of memory devices is higher than a bit error rate of other memory devices of the plurality of memory devices.
16. The method of claim 11 , comprising:
communicating a first control signal to a first memory device among the plurality of memory devices and to a second memory device among the plurality of memory devices, via a first set of a plurality of input/output lines coupling one or more controllers to the first memory device and the second memory device; and
communicating, in parallel, (i) a second control signal to the first memory device via a second set of the plurality of input/output lines, and (ii) a third control signal to the second memory device via a third set of the plurality of input/output lines, wherein the third set of the plurality of input/output lines is coupled to the one or more controllers and the second memory device.
17. An apparatus, comprising:
means for converting data into a codeword having different portions; and
means for transferring the different portions of the codeword to different memory devices among a plurality of memory devices, to store the different portions of the codeword at a first address in the different memory devices,
wherein the first address is a same address in the different memory devices.
18. The apparatus of claim 17 , comprising means for obtaining the first address to store the different portions of the codeword, prior to the transferring.
19. The apparatus of claim 17 , wherein the means for transferring the different portions of the codeword to the different memory devices comprises means for transferring, in parallel, the different portions of the codeword to the different memory devices.
20. The apparatus of claim 17 , wherein the means for transferring comprises means for transferring, in parallel, a first portion of the codeword among the different portions of the codeword to a first memory device via a first set of a plurality of input/output lines of a bus at the first address in the first memory device and a second portion of the codeword among the different portions of the codeword to a second memory device via a second set of the plurality of input/output lines of the bus at the first address in the second memory device.