Data storage system for improving data throughput and decode capabilities
Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.
1. A data storage system, comprising:
a controller;
a plurality of physical non-volatile memory devices; and
a bus comprising a plurality of input/output (I/O) lines,
wherein the controller is configured to:
receive data;
encode the received data into a codeword;
identify an address to store different portions of the codeword; and
transfer, in parallel, the different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices, to store the different portions of the codeword at the identified address in the different physical non-volatile memory devices,
wherein the identified address is a same address in the different physical non-volatile memory devices.
2. The data storage system of claim 1 , wherein a first set of the plurality of I/O lines of the bus is coupled to the controller and a first physical non-volatile memory device of the plurality of physical non-volatile memory devices, and a second set of the plurality of I/O lines of the bus couples the controller and a second physical non-volatile memory device of the plurality of physical non-volatile memory devices.
3. The data storage system of claim 2 , wherein the controller is configured to transfer the different portions of the codeword to the different physical non-volatile memory devices by transferring, in parallel, a first portion of the codeword among the different portions of the codeword to the first physical non-volatile memory device via the first set of the plurality of I/O lines of the bus at the identified address in the first physical non-volatile memory device and a second portion of the codeword among the different portions of the codeword to the second physical non-volatile memory device via the second set of the plurality of I/O lines of the bus at the identified address in the second physical non-volatile memory device.
4. The data storage system of claim 1 , wherein the controller is further configured to:
read, in parallel, the different portions of the codeword from the different physical non-volatile memory devices among the plurality of physical non-volatile memory devices; and
decode the codeword comprising the different portions of the codeword.
5. The data storage system of claim 4 , wherein a bit error rate (BER) of at least one of the plurality of physical non-volatile memory devices is higher than a BER of other physical non-volatile memory devices, and wherein the data storage system is configured to spread the codeword over the plurality of physical non-volatile memory devices to reduce a sensitivity of a decoder to a physical defect in one of the plurality of physical non-volatile memory devices.
6. The data storage system of claim 5 , wherein the other physical non-volatile memory devices are configured to compensate for the higher BER of the at least one of the plurality of physical non-volatile memory devices.
7. The data storage system of claim 6 , wherein the BER of the at least one of the plurality of physical non-volatile memory devices being higher than the BER of the other physical non-volatile memory devices of the plurality of physical non-volatile memory devices allows increasing a production yield.
8. The data storage system of claim 1 , wherein the controller is further configured to:
communicate a first control signal to a first physical non-volatile memory device among the plurality of physical non-volatile memory devices and to a second physical non-volatile memory device among the plurality of physical non-volatile memory devices via a first set of the plurality of I/O lines coupling the controller to the first physical non-volatile memory device and the second physical non-volatile memory device.
9. The data storage system of claim 8 , wherein the first control signal comprises a data write control signal.
10. The data storage system of claim 8 , wherein the controller is further configured to:
communicate, in parallel, a second control signal to the first physical non-volatile memory device via a second set of the plurality of I/O lines, and a third control signal to the second physical non-volatile memory device via a third set of the plurality of I/O lines, wherein the first set of the plurality of I/O lines couples the controller and the first physical non-volatile memory device, and wherein the third set of the plurality of I/O lines couples the controller and the second physical non-volatile memory device.
11. The data storage system of claim 10 , wherein the second and third control signals comprise data read control signals.
12. The data storage system of claim 1 , wherein a flip chip package comprises the controller and the plurality of physical non-volatile memory devices.
13. The data storage system of claim 1 , wherein the controller is configured to use a same command to store the different portions of the codeword at the identified address which is a same physical address in the different physical non-volatile memory devices.
14. The data storage system of claim 1 , comprising a separate data line coupled between the controller and the different physical non-volatile memory devices, wherein the controller is configured to transfer, in parallel, a slow control signal to the different physical non-volatile memory devices via the separate data line, wherein a first speed of transmission via the separate data line is slower than a second speed of transmission via the bus.
15. A method comprising,
receiving data;
encoding the received data into a codeword;
identifying an address to store different portions of the codeword; and
transferring, in parallel, the different portions of the codeword to different physical non-volatile memory devices among a plurality of physical non-volatile memory devices, to store the different portions of the codeword at the identified address in the different physical non-volatile memory devices,
wherein the identified address is a same physical address in the different physical non-volatile memory devices.
16. The method of claim 15 , further comprising:
transferring, in parallel, a first portion of the codeword among the different portions of the codeword to a first physical non-volatile memory device via a first set of a plurality of I/O lines of a bus at the identified address in the first physical non-volatile memory device and a second portion of the codeword among the different portions of the codeword to a second physical non-volatile memory device via a second set of the plurality of I/O lines of the bus at the identified address in the second physical non-volatile memory device, wherein the identified address in the first physical non-volatile memory device and the identified address in the second physical non-volatile memory device is the same physical address.
17. The method of claim 15 , further comprising:
reading, in parallel, the different portions of the codeword from the different physical non-volatile memory devices among the plurality of physical non-volatile memory devices; and
decoding the codeword comprising the different portions of the codeword.
18. The method of claim 17 , wherein spreading the codeword over the plurality of physical non-volatile memory devices reduces a sensitivity of a decoder to a physical defect in one of the plurality of physical non-volatile memory devices.
19. The method of claim 15 , wherein a BER of at least one of the plurality of physical non-volatile memory devices is higher than a BER of other physical non-volatile memory devices, wherein the other physical non-volatile memory devices compensate for the higher BER of the at least one of the plurality of physical non-volatile memory devices.
20. The method of claim 19 , wherein utilizing the at least one of the plurality of physical non-volatile memory devices with the higher BER allows increasing a production yield.
21. The method of claim 15 , wherein transferring different portions of the codeword, in parallel, increases throughput over a bus without changes to a bus clock rate.
22. The method of claim 15 , further comprising:
communicating a first control signal to a first physical non-volatile memory device among the plurality of physical non-volatile memory devices and to a second physical non-volatile memory device via a first set of a plurality of I/O lines of a bus coupling a controller to the first physical non-volatile memory device and the second physical non-volatile memory device.
23. The method of claim 22 , wherein the first control signal comprises a data write control signal.
24. The method of claim 23 , further comprising:
communicating, in parallel, a second control signal to the first physical non-volatile memory device via a second set of the plurality of I/O lines, and a third control signal to the second physical non-volatile memory device via a third set of the plurality of I/O lines, wherein the first set of the plurality of I/O lines couples the controller and the first physical non-volatile memory device, and wherein the third set of the plurality of I/O lines couples the controller and the second physical non-volatile memory device.
25. The method of claim 24 , wherein the second and third control signals comprise data read control signals.
26. A data storage system, comprising:
a plurality of physical non-volatile memory devices;
a bus comprising a plurality of input/output (I/O) lines;
means for identifying an address to store different portions of a codeword; and
means for transferring, in parallel, the different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices, to store the different portions of the codeword at the identified address in the different physical non-volatile memory devices,
wherein the identified address is a same address in the different physical non-volatile memory devices.
27. The data storage system of claim 26 , further comprising:
means for reading, in parallel, the different portions of the codeword from the different physical non-volatile memory devices among the plurality of physical non-volatile memory devices; and
means for decoding the codeword comprising the different portions of the codeword.
28. The data storage system of claim 1 ,
wherein the plurality of physical non-volatile memory devices are physical dies, and
wherein the physical dies are grouped into a single logical non-volatile memory device.
29. The data storage system of claim 28 , wherein the controller is configured to identify, as the identified address, a next available address of the single logical non-volatile memory device, based on block and page management data.