IP Library Granted Patent US 12,601,779
Granted Patent B2
US 12,601,779 · App. 18/504,413 · Granted Apr 14, 2026

Determining a back drilling depth for a printed circuit board using a printed circuit board test coupon

Inventor: John Patrick Burke (San Jose, CA)
Assignee: Sandisk Technologies, Inc.
G01R31/2806
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Quick Facts
Patent No.
US 12,601,779
App. No.
18/504,413
Granted
Apr 14, 2026
Kind
B2
Abstract

A PCB test coupon is used to determine a back drilling depth to remove a stub from a PCB. A number of conductors are placed at various layers within the PCB test coupon. Vias connect each end of a conductor to a surface layer of the PCB test coupon and form test points on the surface layer of the PCB test coupon. To determine a depth of each conductor, an inductive test probe is placed on the surface layer of the PCB test coupon. The inductive test probe generates and emits an alternating magnetic field which acts on the conductors and causes a crosstalk voltage to occur across the test points. The voltage across the test points is proportional to the distance of the conductors in each layer of the PCB test coupon.

Claims (47)

1 . A printed circuit board (PCB) test coupon, comprising:

a first layer comprising a first conductor;

a second layer positioned beneath the first layer and comprising a second conductor;

a first via extending from a top surface of the first layer to a first side of the first conductor;

a first test point provided on the top surface of the first layer and associated with the first via;

a second via extending from the top surface of the first layer to a second side of the first conductor; and

a second test point provided on the top surface of the first layer and associated with the second via, wherein when an inductive probe is placed on the top surface of the first layer and a current is passed through the probe, a magnetic field is generated and a voltage reading across the first test point and the second test point is associated with a depth of the first conductor.

2 . The PCB test coupon of claim 1 , further comprising:

a third via extending from the top surface of the first layer to a first side of the second conductor;

a third test point provided on the top surface of the first layer and associated with the third via;

a fourth via extending from the top surface of the first layer to a second side of the second conductor; and

a fourth test point provided on the top surface of the first layer and associated with the fourth via, wherein when the inductive probe is placed on the top surface of the first layer and the current is passed through the inductive probe, the magnetic field is generated and a voltage reading across the third test point and the fourth test point is associated with a depth of the second conductor.

3 . The PCB test coupon of claim 1 , wherein a frequency of a signal provided to the inductive probe is based, at least in part, on a design of the PCB test coupon.

4 . The PCB test coupon of claim 1 , wherein the depth of at least one of the first conductor and the second conductor indicates a drilling depth of a back drilling process to be performed on a PCB associated with the PCB test coupon.

5 . The PCB test coupon of claim 1 , wherein a waveform of a signal provided to the inductive probe is based, at least in part, on a design of the PCB test coupon.

6 . A method, comprising:

placing a probe on a top surface of a printed circuit board (PCB) test coupon;

passing a current through the probe;

determining a signal between a first test point on the top surface of the PCB test coupon and a second test point on the top surface of the PCB test coupon, the first test point being associated with a first via that extends from the top surface of the PCB test coupon to a first side of a first conductor on a first layer of the PCB test coupon and the second test point being associated with a second via that extends from the top surface of the PCB test coupon to a second side of the first conductor on the first layer of the PCB test coupon; and

determining, based at least in part, on the signal between the first test point and the second test point, a back drilling depth associated with at least one of the first via and the second via.

7 . The method of claim 6 , wherein the probe is an inductive probe.

8 . The method of claim 6 , wherein the current is an alternating current.

9 . The method of claim 6 , wherein the signal is a voltage reading and wherein a value of the voltage reading is proportional to a depth of the first conductor on the first layer of the PCB test coupon.

10 . The method of claim 6 , further comprising:

determining a signal between a third test point on the top surface of the PCB test coupon and a fourth test point on the top surface of the PCB test coupon, the third test point being associated with a third via that extends from the top surface of the PCB test coupon to a first side of a second conductor on a second layer of the PCB test coupon and the fourth test point being associated with a fourth via that extends from the top surface of the PCB test coupon to a second side of the second conductor on the second layer of the PCB test coupon; and

determining, based at least in part, on the signal between the third test point and the fourth test point, a back drilling depth associated with at least one of the third via and the fourth via.

11 . The method of claim 6 , wherein a waveform of the current is based, at least in part, on a design of the PCB test coupon.

12 . The method of claim 6 , wherein a frequency of the current is based, at least in part, on a design of the PCB test coupon.

13 . The method of claim 6 , further comprising generating a characterization table for the PCB test coupon based, at least in part, on the signal between the first test point and the second test point and a determined depth of the first conductor.

14 . A method, comprising:

placing a probe on a top surface of a printed circuit board (PCB) test coupon, the PCB test coupon being associated with a PCB;

determining a back drilling depth for a via associated with a first layer of the PCB, the back drilling depth being determined by:

passing a current through the probe;

determining a strength of a signal between a first test point on the top surface of the PCB test coupon and a second test point on the top surface of the PCB test coupon, the first test point being associated with a first via that extends from the top surface of the PCB test coupon to a first side of a first conductor on a first layer of the PCB test coupon and the second test point being associated with a second via that extends from the top surface of the PCB test coupon to a second side of the first conductor on the first layer of the PCB test coupon; and

identifying the back drilling depth by comparing the strength of the signal to a depth characterization table associated with the PCB; and

back drilling the via associated with the first layer of the PCB to the back drilling depth.

15 . The method of claim 14 , wherein the probe is an inductive probe.

16 . The method of claim 14 , wherein the current is an alternating current.

17 . The method of claim 14 , wherein the signal is a voltage reading and wherein a value of the voltage reading is proportional to a depth of the first conductor on the first layer of the PCB test coupon.

18 . The method of claim 14 , further comprising:

determining a back drilling depth for a via associated with a second layer of the PCB, the back drilling depth for the via associated with the second layer being determined by:

passing a current through the probe;

determining a strength of a signal between a third test point on the top surface of the PCB test coupon and a fourth test point on the top surface of the PCB test coupon, the third test point being associated with a third via that extends from the top surface of the PCB test coupon to a first side of a second conductor on a second layer of the PCB test coupon and the fourth test point being associated with a fourth via that extends from the top surface of the PCB test coupon to a second side of the second conductor on the second layer of the PCB test coupon; and

identifying the back drilling depth by comparing the strength of the signal to a depth characterization table associated with the PCB; and

back drilling the via associated with the second layer of the PCB to the back drilling depth.

19 . The method of claim 14 , wherein a waveform of the current is based, at least in part, on a design of the PCB test coupon.

20 . The method of claim 14 , wherein a frequency of the current is based, at least in part, on a design of the PCB test coupon.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2023
From: BURKE, JOHN PATRICK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065499/0115 →
Continuity (1)
Related Publication 20250147097A1 · May 8, 2025
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