Programming scheme for improved voltage distribution in solid-state memory
View Patent ↗Systems and methods are disclosed for reducing programming interference in solid-state memory using a program suspend command. A data storage system includes a non-volatile memory array including a plurality of non-volatile memory devices and a controller configured to partially program a first cell coupled to a first word line. When a programming criterion associated with the first cell is met, the controller executes a program suspend command after which a second cell coupled to the first word line is at least partially programmed. Programming of the first cell is resumed following said at least partial programming of the second cell.
1. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory devices; and
a controller configured to:
partially program a first cell coupled to a first word line;
determine that a programming criterion associated with the first cell is met;
execute a program suspend command;
at least partially program a second cell coupled to the first word line following execution of the program suspend command;
resume programming of the first cell following said at least partial programming of the second cell.
2. The data storage device of claim 1 , wherein the second and first cells are disposed adjacent to one another on the word line.
3. The data storage device of claim 1 , wherein the controller is further configured to at least partially reduce bit-line-to-bit-line interference between the first and second cells at least in part by executing the program suspend command.
4. The data storage device of claim 1 , wherein the controller is further configured to program the first and second cells in accordance with a half bit line (HBL) programming scheme.
5. The data storage device of claim 1 , wherein the programming criterion is met when a program verify command passes.
6. The data storage device of claim 1 , wherein the programming criterion is met when the controller has applied a predetermined number of program pulses to the first cell.
7. The data storage device of claim 1 , wherein the programming criterion is met when the controller has applied a predetermined program voltage level to the first cell.
8. The data storage device of claim 1 , wherein the controller is further configured to resume the programming of the first cell after programming of the second cell is completed.
9. The data storage device of claim 1 , wherein the controller is further configured to complete programming of the first cell when it resumes programming of the first cell.
10. The data storage device of claim 1 , wherein the first cell is associated with an even page and the second cell is associated with an odd page.
11. The data storage device of claim 1 , wherein the first cell is associated with an odd page and the second cell is associated with an even page.
12. The data storage device of claim 1 , wherein the first word line is coupled to a first plurality of cells and a second plurality of cells interleaved with the first plurality of cells, wherein the controller is configured to program the first cell by programming the first plurality of cells and to program the second cell by programming the second plurality of cells.
13. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory devices; and
a controller configured to:
partially program a first cell coupled to a first word line;
determine that a programming criterion associated with the first cell is met;
execute a program suspend command;
partially program a second cell coupled to a second word line; and
resume programming of the first cell after said partial programming of the second cell.
14. The data storage device of claim 13 , wherein the controller is further configured to complete programming of the first cell after said partial programming of the second cell and to complete programming of the second cell after completion of the programming of the first cell.
15. The data storage device of claim 14 , wherein the controller is further configured to partially program a third cell coupled to a third word line after completion of the programming of the first cell and before completion of the programming of the second cell.
16. The data storage device of claim 13 , wherein the controller is further configured to program the first and second cells in accordance with an all bit line (ABL) programming scheme.
17. The data storage device of claim 13 , wherein the controller is configured to program the first and second cells using full-sequence programming.
18. The data storage device of claim 13 , wherein the programming criterion is met when a program verify command passes.
19. The data storage device of claim 13 , wherein the programming criterion is met when the controller has applied a predetermined number of program pulses to the first cell.
20. The data storage device of claim 13 , wherein the programming criterion is met when the controller has applied a predetermined program voltage level to the first cell.
21. The data storage device of claim 13 , wherein the first word line is adjacent to the second word line in the non-volatile memory array.
22. The data storage device of claim 13 , wherein the controller is configured to at least partially reduce word-line-to-word-line interference between the first and second word lines at least in part by executing the program suspend command.
23. A method of programming data in a data storage system comprising a non-volatile memory array, the method comprising:
partially programming a first cell coupled to a first word line;
determining that a programming criterion associated with the first cell has been met;
executing a program suspend command;
at least partially programming a second cell coupled to the first word line following execution of the program suspend command; and
resuming programming of the first cell following said at least partial programming of the second cell;
wherein the method is performed under the control of a controller of the data storage system.
24. The method of claim 23 , wherein the second and first cells are disposed adjacent to one another on the word line.
25. The method of claim 23 , further comprising at least partially reducing bit-line-to-bit-line interference between the first and second cells at least in part by said executing the program suspend command.
26. The method of claim 23 , further comprising programming the first and second cells in accordance with a half bit line (HBL) programming scheme.
27. The method of claim 23 , wherein the programming criterion is met when a program verify command passes.
28. The method of claim 23 , wherein the programming criterion is met when a predetermined number of program pulses have been applied to the first cell.
29. The method of claim 23 , wherein the programming criterion is met when a predetermined program voltage level has been applied to the first cell.
30. The method of claim 23 , further comprising resuming the programming of the first cell after programming of the second cell is completed.
31. The method of claim 23 , further comprising completing programming of the first cell when resuming programming of the first cell.
32. The method of claim 23 , wherein the first cell is associated with an even page and the second cell is associated with an odd page.
33. The method of claim 23 , wherein the first cell is associated with an odd page and the second cell is associated with an even page.
34. The method of claim 23 , wherein the first word line is coupled to a first plurality of cells and a second plurality of cells interleaved with the first plurality of cells, wherein programming the first cell comprises programming the first plurality of cells and programming the second cell comprises programming the second plurality of cells.
35. A method of programming data in a data storage system comprising a non-volatile memory array, the method comprising:
partially programming a first cell coupled to a first word line;
determining that a programming criterion associated with the first cell has been met;
executing a program suspend command;
partially programming a second cell coupled to a second word line; and
resuming programming of the first cell after said partial programming of the second cell;
wherein the method is performed under the control of a controller of the data storage system.
36. The method of claim 35 , further comprising completing programming of the first cell after said partial programming of the second cell and to completing programming of the second cell after completion of the programming of the first cell.
37. The method of claim 36 , further comprising partially programing a third cell coupled to a third word line after completing the programming of the first cell and before completing the programming of the second cell.
38. The method of claim 35 , wherein said partially programing the first and second cells is performed in accordance with an all bit line (ABL) programming scheme.
39. The method of claim 35 , wherein said partially programming the first and second cells is performed using full-sequence programming.
40. The method of claim 35 , wherein determining that the programming criterion associated with the first cell has been met comprises determining that a program verify command has passed.
41. The method of claim 35 , wherein the programming criterion is met when a predetermined number of program pulses has been applied to the first cell.
42. The method of claim 35 , wherein the programming criterion is met when the controller has applied a predetermined program voltage level to the first cell.
43. The method of claim 35 , wherein the first word line is adjacent to the second word line in the non-volatile memory array.
44. The method of claim 35 , further comprising reducing word-line-to-word-line interference between the first and second word lines at least in part by said executing the program suspend command.