IP Library Granted Patent US 9,887,004
Granted Patent B2
US 9,887,004 · App. 15/194,678 · Granted Feb 6, 2018

Bi-directional RRAM decoder-driver

Inventors: James Edwin O'Toole (Boise, ID); Ward Parkinson (Boise, ID); Daniel Robert Shepard (North Hampton, NH); Thomas Michael Trent (Tucson, AZ)
Assignee: Western Digital Technologies, Inc.
G11C13/0069G11C11/00G11C13/0004G11C13/0007G11C13/0023H01L27/2427H01L27/2463H01L45/085H01L45/1233H01L45/146
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Quick Facts
Patent No.
US 9,887,004
App. No.
15/194,678
Granted
Feb 6, 2018
Kind
B2
Abstract

The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

Claims (35)

1. A method for creating an inverter, comprising:

selecting a word line;

applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;

selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to a second state, wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein at least one of i) the applying the first voltage to the first inverter line provides a third voltage to an ovonic threshold switch (OTS) coupled with the word line and the first inverter line or ii) applying the second voltage to the second inverter line provides a fourth voltage to an ovonic threshold switch (OTS) coupled with the bit line and the second inverter line.

2. The method of claim 1 , wherein the first inverter line is coupled to the word line.

3. The method of claim 1 , wherein the second inverter line is coupled to the bit line.

4. The method of claim 1 , wherein the selecting the bit line corresponding to the first state is through an n-channel.

5. The method of claim 1 , wherein the applying the first voltage to the first inverter line causes a filament formation.

6. The method of claim 5 , wherein the applying the second voltage to the second inverter line destroys the filament formation.

7. The method of claim 5 , wherein the filament formation is formed within a memory cell.

8. The method of claim 6 , wherein the memory cell comprises a RRAM material selected from the group comprising:

zinc oxide (ZnO), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), tantalum oxide (TaO 2 ), vanadium oxide (VO 2 ), tungsten oxide (WO 2 ), zirconium oxide (ZrO 2 ), copper oxide, nickel oxide, or combinations and mixtures thereof.

9. A method for creating an inverter, comprising:

selecting a word line;

applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;

selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, where the applying the second voltage to the second inverter line includes: actively driving the second inverter line to the second state through a p-channel transistor.

10. The method of claim 9 , wherein the p-channel transistor is coupled to a power supply via a wired connection.

11. A method for creating an inverter, comprising:

selecting a word line;

applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;

selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein the applying the first voltage to the first inverter line provides a third voltage to an ovonic threshold switch (OTS) coupled with the word line and the first inverter line.

12. The method of claim 11 , wherein the providing the third voltage causes a filament formation.

13. The method of claim 11 , wherein the third voltage is greater than the first voltage.

14. The method of claim 11 , wherein the third voltage turns on the OTS.

15. A method for creating an inverter, comprising:

selecting a word line;

applying a first voltage to a first inverter line to bring the first inverter line to ground, wherein the first voltage causes the word line to be brought to a first state;

selecting a bit line corresponding to the first state; and

applying a second voltage to a second inverter line to bring the second inverter line to wherein the second voltage causes the bit line to correspond to the second state, and wherein the first state is opposite to the second state, wherein the applying the second voltage to the second inverter line provides a fourth voltage to an ovonic threshold switch (OTS) coupled with the bit line and the second inverter line.

16. The method of claim 15 , wherein the providing the fourth voltage causes a filament destruction.

17. The method of claim 15 , wherein the fourth voltage is greater than the second voltage.

18. The method of claim 15 , wherein the fourth voltage turns on the OTS.

Assignments (12)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2016
From: O'TOOLE, JAMES EDWIN; PARKINSON, WARD; SHEPARD, DANIEL ROBERT; TRENT, THOMAS MICHAEL
To: HGST NETHERLANDS B.V.
Reel/Frame 039026/0845 →
Continuity (1)
Related Publication 20170372781A1 · Dec 28, 2017