Speculative pre-fetching of flash translation layer tables for use with solid state systems
The present disclosure describes technologies and techniques for use by a data storage controller of a non-volatile memory (NVM) system. In various examples, the controller is configured to perform speculative pre-fetching from a flash translation layer (FTL) table that relates logical addresses to physical locations in the NVM. In some examples, hardware within the controller fetches an entry from an external FTL table based on a provisional FTL address determined using a simplified (quick) address determination procedure and caches the entry internally. This is referred to as speculative pre-fetch. An FTL processor also determines the address of the FTL entry using a full (slower) firmware-based procedure. The FTL processor applies its firmware-computed address to the cache to determine if the entry is cached and, if so, the entry is retrieved from the cache. Otherwise, the entry is retrieved from the external FTL table. In this manner, latency can be reduced.
1. A data storage system for use with a host device, comprising:
a non-volatile memory (NVM) device;
a cache; and
a data storage controller having a processing system configured to
apply an input logical address to a first determination component to convert the input logical address to a first value for accessing a mapping component that maps logical addresses to corresponding NVM physical addresses in the NVM device,
retrieve an entry from the mapping component that corresponds to the first value and caching the retrieved entry in the cache, wherein the retrieved entry is not correct for at least some input logical address values,
apply the input logical address to a second determination component to convert the input logical address to a second value for accessing the mapping component, wherein second determination component is configured to implement at least some computation procedures omitted from the first determination component, and wherein second value is correct, and
access the cache to determine if an entry corresponding to the second value is within the cache and, if so, fetching the entry from the cache, and, if not, fetching the entry from the mapping component using the second value to locate the entry within the mapping component.
2. The data storage system of claim 1 , wherein the mapping component is a component of one or more of the NVM device, the data storage controller, and the host device.
3. The data storage system of claim 1 , wherein the mapping component is a flash translation layer (FTL) table, the first and second values are FTL table addresses configured to specify address locations for entries within the FTL table, and the cache is an FTL cache.
4. The data storage system of claim 1 , wherein the first determination component is a hardware (HW) component of the data storage controller and the second determination component is a firmware (FW) component of the data storage controller.
5. The data storage system of claim 1 , wherein the mapping component is configured in a first memory, and the cache is configured in a second memory.
6. The data storage system of claim 1 , wherein the first determination component is a front end (FE) component of the data storage controller, and wherein the second determination component is a back end (BE) of the data storage controller.
7. The data storage system of claim 1 , wherein the NVM device comprises a NAND storage device.
8. A data storage controller for use with a non-volatile memory (NVM) device, comprising:
a first processor configured to determine a first value from an input logical address for accessing a mapping table, the mapping table configured to map logical addresses to NVM physical addresses in the NVM device;
a second processor configured to determine a second value from the input logical address for accessing the mapping table, wherein second processor is configured to implement at least some computation procedures omitted from the first processor, and wherein first value determined by the first processor is incorrect for at least some input logical address whereas the second value is correct;
a cache controller configured to fetch an entry from the mapping table that corresponds to the first value and cache the fetched entry in a cache, wherein the fetched entry is not correct for the at least some input logical address values; and
a third processor configured to access the cache to determine if an entry corresponding to the second value is within the cache and, if so, to obtain the entry from the cache, and, if not, to obtain the entry from the mapping component using the second value.
9. The data storage controller of claim 8 , wherein the mapping table is a flash translation layer (FTL) table, the first and second values are FTL table addresses configured to specify address locations for entries within the FTL table, and the cache is an FTL cache.
10. The data storage system of claim 9 , wherein the first processor is configured to provide a first FTL address that does not correspond to a particular FTL table entry in the FTL table that maps the input logical address to the NVM physical address.
11. The data storage system of claim 10 , wherein the second processor is configured to provide a second FTL table address that corresponds to the particular FTL table entry that maps the input logical address to the NVM physical address.
12. The data storage controller of claim 8 , wherein the first processor is a hardware (HW) processor and the second processor is a firmware (FW) processor.
13. The data storage controller of claim 8 , wherein the mapping table is configured in a first memory device, and the cache is configured in a second memory device, the second memory configured to operate faster than the first memory.
14. The data storage controller of claim 13 , wherein the first memory device that includes the mapping table is a dynamic random access memory (DRAM), and the second memory device that includes the cache is a static random access memory (SRAM).
15. The data storage controller of claim 14 , wherein the first memory device that includes the mapping table is a host memory buffer (HMB) of a host device, and the second memory device that includes the cache is a static random access memory (SRAM).
16. The data storage controller of claim 13 , wherein the first memory device that includes the mapping table is a NAND storage component within the NVM device, and the second memory device that includes the cache is a static random access memory (SRAM).
17. The data storage controller of claim 8 , wherein the first processor is a front end (FE) processor of the data storage controller, and wherein the second processor is a back end (BE) processor of the data storage controller.
18. The data storage controller of claim 8 , wherein the third processor is a flash translation layer (FTL) processor that is separate from the first processor.
19. The data storage controller of claim 8 , wherein the NVM device comprises a NAND storage device.
20. A method for use by a data storage system having a data storage controller and a non-volatile memory (NVM) device, comprising:
determining, using an input logical address and a first determination procedure, a first value for accessing a mapping component that maps logical addresses to corresponding NVM physical addresses in the NVM device;
fetching an entry from the mapping component that corresponds to the first value and caching the fetched entry in a cache, wherein the fetched entry is not correct for at least some input logical address values;
determining, using the input logical address and a second determination procedure, a second value for accessing the mapping component, wherein the second determination procedure includes at least some computation procedures omitted by the first determination procedure and wherein the second value is correct; and
accessing the cache to determine if an entry corresponding to the second value is within the cache and, if so, fetching the entry from the cache, and, if not, fetching the entry from the mapping component using the second value to locate the entry within the mapping component.
21. The method of claim 20 , wherein the mapping component is a flash translation layer (FTL) table, the first and second values are FTL table addresses configured to specify address locations for entries within the FTL table, and the cache is an FTL cache.
22. The method of claim 21 , wherein the first determination procedure is a provisional determination procedure and the first value is a provisional address to be applied to the FTL table that does not correspond to a particular FTL table entry that maps the input logical address to the NVM physical address.
23. The method of claim 22 , wherein the second determination procedure is a full determination procedure and the second value is the FTL table address that corresponds to the particular FTL table entry that maps the input logical address to the NVM physical address.
24. The method of claim 20 , wherein the mapping component is stored in a first memory, and the cache is stored in a second memory, the second memory being faster than the first memory.
25. The method of claim 20 , wherein fetching the entry from the mapping component and applying the input logical address to a second determination procedure are initiated concurrently.
26. The method of claim 20 ,
wherein the input logical address is received from a host device along with a corresponding memory access command directed to the input logical address, and
wherein the input logical address is applied to a hardware component to determine the first value, and the corresponding memory access command is applied to a flash translation layer (FTL) processor that is separate from the hardware component to determine the second address.
27. The method of claim 26 , wherein the entry is cached before the corresponding memory access command is applied to the FTL processor.
28. An apparatus for use in a data storage system having a non-volatile memory (NVM) device, comprising:
means for converting an input logical address using a first conversion procedure to a first value for accessing a mapping component that maps logical addresses to corresponding NVM physical addresses in the NVM device;
means for converting the input logical address using a second conversion procedure to a second value for accessing the mapping component, wherein the means for converting the input logical address using the first conversion procedure employs at least some computational procedures omitted from the means for converting the input logical address using the second conversion procedure, and wherein the first value is incorrect for at least some input logical address whereas the second value is correct;
means for obtaining an entry from the mapping component that corresponds to the first value;
means for caching the obtained entry in a cache;
and
means for accessing the cache to determine if an entry corresponding to the second value is within the cache and, if so, for fetching the entry from the cache, and, if not, for fetching the entry from the mapping component using the second value to locate the entry within the mapping component.
29. The apparatus of claim 28 , wherein the mapping component is a flash translation layer (FTL) table, the first and second values are FTL table addresses configured to specify address locations for entries within the FTL table, and the cache is an FTL cache.
30. The apparatus of claim 29 , wherein the NVM device comprises a NAND storage device.