Fast secure erase in a flash system
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.
1. A machine-implemented method, comprising:
receiving a fast erase signal to erase one or more groups of flash memory cells in a flash memory device;
switching, by a flash memory controller, operating parameters of the flash memory device from first parameters corresponding to a first erase mode for erasing the one or more groups of flash memory cells to second parameters corresponding to a second erase mode for erasing the one or more groups of flash memory cells based on receiving the fast erase signal, the second parameters comprising an erase pulse voltage based on a current number of cycles for the one or more groups of flash memory cells, wherein the flash memory device is configured to operate in the first erase mode by default; and
instructing the flash memory device to perform an erase operation using a single erase pulse at the erase pulse voltage to erase the one or more groups of flash memory cells.
2. The method of claim 1 , further comprising:
verifying that the erase operation was completed using the single erase pulse.
3. The method of claim 2 , further comprising:
writing random data to the one or more groups of flash memory cells after the erase operation is completed.
4. The method of claim 1 , wherein switching the operating parameters comprises:
indexing a lookup table by the current number of cycles to obtain the erase pulse voltage from the lookup table.
5. The method of claim 1 , wherein an erase operation in the first erase mode is an incremental stepping pulse erase operation.
6. The method of claim 1 , wherein each group of flash memory cells is arranged and addressed by the flash memory controller as a memory block, the method further comprising:
in response to receiving the fast erase signal, instructing the flash memory device to perform the erase operation, according to the second parameters, for all memory blocks in the flash memory device.
7. The method of claim 6 , further comprising:
in response to receiving the fast erase signal, switching operating parameters of a plurality of flash memory devices from the first parameters to the second parameters, and instructing each of the plurality of flash memory devices to perform erase operations in parallel, according to the second parameters, to erase all memory blocks in each respective flash memory device.
8. A data storage system, comprising:
a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and
a controller coupled to the plurality of flash memory devices, wherein the controller is configured to:
receive a fast erase signal for erasing one or more respective memory blocks of one or more of the plurality of flash memory devices;
switch operating parameters of the one or more of the flash memory devices from first parameters corresponding to a first erase mode for erasing the one or more respective memory blocks to second parameters corresponding to a second erase mode for erasing the one or more respective memory blocks based on receiving the fast erase signal, the second parameters comprising an erase pulse voltage based on a current number of cycles for the one or more respective memory blocks, wherein the flash memory devices are configured to operate in the first erase mode by default; and
instruct the one or more of the flash memory devices to perform an erase operation using a single erase pulse at the erase pulse voltage to erase the one or more respective memory blocks.
9. The data storage system of claim 8 , wherein the controller is further configured to:
verify the erase operation was completed using the single erase pulse.
10. The data storage system of claim 8 , wherein switching the operating parameters comprises:
indexing a lookup table by the current number of cycles to obtain the erase pulse voltage from the lookup table.
11. The data storage system of claim 8 , wherein an erase operation in the first erase mode is an incremental stepping pulse erase operation.
12. The data storage system of claim 8 , wherein the controller is further configured to:
write random data to the one or more respective memory blocks after the erase operation is completed.
13. The data storage system of claim 8 , wherein the controller is further configured to:
in response to receiving the fast erase signal, instruct each of the one or more of the flash memory devices to perform the erase operation, according to the second parameters, for all memory blocks in the flash memory device.
14. The data storage system of claim 13 , wherein the controller is further configured to:
in response to receiving the fast erase signal, switch operating parameters of the plurality of flash memory devices from the first parameters to the second parameters, and instruct each of the plurality of flash memory devices to perform erase operations in parallel, according to the second parameters, to erase all memory blocks in each respective flash memory device.
15. A machine-implemented method, comprising:
receiving a fast erase signal to erase a plurality of memory blocks in a flash memory device;
switching, by a flash memory controller, operating parameters of the flash memory device from first parameters corresponding to a first erase mode to second parameters corresponding to a second erase mode based on receiving the fast erase signal, the first erase mode erasing memory cells in the flash memory device using a plurality of erase pulses and the second erase mode erasing the memory cells using a single erase pulse; and
in response to receiving the fast erase signal, instructing the flash memory device to perform an erase operation, using the second parameters, to erase all of the plurality of memory blocks in the flash memory device.
16. The machine-implemented method of claim 15 , further comprising:
verifying that the erase operation was completed using the single erase pulse.
17. The machine-implemented method of claim 15 , further comprising:
writing random data to the plurality of memory blocks after the erase operation is completed.
18. A data storage system, comprising:
a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and
a controller coupled to the plurality of flash memory devices, wherein the controller is configured to:
erase memory cells of one or more of the flash memory devices using a first erase mode or a second erase mode, the first erase mode for erasing memory cells using a plurality of erase pulses and the second erase mode for erasing the memory cells using a single erase pulse;
receive a fast erase signal for erasing all memory blocks of the one or more of the plurality of flash memory devices according to the second erase mode;
switch operating parameters of the one or more of the flash memory devices from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode based on receiving the fast erase signal; and
instruct the one or more of the flash memory devices to perform an erase operation, using the second parameters, to erase all memory blocks of the one or more of the plurality of flash memory devices.
19. The data storage system of claim 18 , wherein the controller is further configured to:
verify that the erase operation was completed using the single erase pulse.
20. The data storage system of claim 18 , wherein the controller is further configured to:
write random data to the plurality of memory blocks after the erase operation is completed.