Overlapping write schemes for cross-point non-volatile memory devices
A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second write operation. The first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state. The control module may be further configured to execute the first write operation by causing an electrical pulse to be applied to a first cell of the NVM device to place the first cell in the relatively low-resistance state. The control module may be further configured to execute the second write operation by causing an electrical pulse to be applied to a second cell of the NVM device before the first electrical pulse has concluded. A single tile of the NVM device includes the first cell and the second cell.
1. A storage device comprising:
an interface;
a non-volatile memory (NVM) device; and
a control module, the control module configured to:
receive a plurality of write operations from the interface, wherein the plurality of write operations includes at least a first write operation and a second write operation, wherein the first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state;
execute the first write operation by causing a first electrical pulse to be applied to a first cell to place the first cell of an NVM device in the relatively low-resistance state; and
execute the second write operation by causing a second electrical pulse to be applied to a second cell of the NVM device and to be overlapping with application of the first electrical pulse and before the first electrical pulse has concluded, wherein a single tile of the NVM device includes the first cell and the second cell.
2. The storage device of claim 1 , wherein the second write operation includes a RESET operation configured to put the second cell in a relatively high-resistance state, wherein the control module is further configured to:
determine that a current of the first electrical pulse satisfies a triggering threshold after applying the first electrical pulse to the first cell, wherein the triggering threshold includes the current of the first electrical pulse decaying to a predetermined percent of the maximum current of the second electrical pulse, wherein the control module causes the second electrical pulse to be applied to the second cell is in response to the current of the first electrical pulse satisfying the triggering threshold.
3. The storage device of claim 2 , wherein the control module is further configured to cause the first electrical pulse to be terminated in response to detecting that the current of the first electrical pulse satisfies the triggering threshold.
4. The storage device of claim 1 , wherein the second write operation includes a RESET operation configured to put the second cell in a relatively high-resistance state, wherein the control module is further configured to:
determine that an amount of time elapsed since the first electrical pulse was applied satisfies a termination threshold after applying the first electrical pulse to the first cell, wherein the termination threshold includes an amount of time that it takes for a current of the first electrical pulse to decay to twenty percent of the maximum current of the second electrical pulse; and
cause the first electrical pulse to be terminated in response to detecting that the amount of time elapsed satisfies the termination threshold.
5. The storage device of claim 1 , wherein the second write operation includes a second SET operation configured to put the second cell in a relatively low-resistance state, wherein the control module is further configured to:
determine that an amount of time elapsed since the first electrical pulse was applied satisfies a triggering threshold after applying the first electrical pulse to the first cell, wherein the triggering threshold includes an amount of time that it takes for a current of the first electrical pulse to decay to twenty percent of a peak current of the first electrical pulse; and
cause the second electrical pulse to be applied to the second cell in response to the amount of time elapsed satisfying the triggering threshold.
6. The storage device of claim 1 , further comprising a reordering module, wherein the first write operation and the second write operation are from a plurality of write operations that are scheduled to be written to the NVM device, wherein the plurality of write operations include both SET operations configured to put respective cells of the tile in a relatively low-resistance state and RESET operations configured to put respective cells of the tile in a relatively high-resistance state, wherein the reordering module is further configured to:
reorder, before the control module causes the first electrical pulse to be applied to the first cell, write operations of the plurality of write operations such that write operations that include SET operations configured to put respective cells into relatively low-resistance state are executed prior to write operations that include RESET operations configured to put respective cells into relatively high-resistance states.
7. The storage device of claim 1 , wherein the first cell and the second cell share either a bit line or a word line.
8. The storage device of claim 1 , wherein the NVM device comprises a cross-point NVM device.
9. The storage device of claim 1 , wherein the NVM device includes the control module.
10. The storage device of claim 1 , wherein the storage device further comprises a controller, wherein the controller includes the control module.
11. A method of managing write operations to a non-volatile memory (NVM) device, the method comprising:
receiving a first write operation, wherein the first write operation comprises a SET operation, and wherein a SET operation is configured to place a cell of the NVM device in a relatively low-resistance state;
receiving a second write operation;
applying a first electrical pulse to a first cell to place the first cell of the NVM device in the relatively low-resistance state; and
applying a second electrical pulse to a second cell of the NVM device such that the second electrical pulse overlaps the first electrical pulse, wherein a single tile of the NVM device includes the first cell and the second cell.
12. The method of claim 11 , wherein the second write operation includes a RESET operation configured to put the second cell in a relatively high-resistance state, the method further comprising:
after applying the first electrical pulse to the first cell, determining that a current of the first electrical pulse satisfies a triggering threshold, wherein the triggering threshold includes the current of the first electrical pulse decaying to a predetermined percent of the maximum current of the second electrical pulse, wherein the applying the second electrical pulse to the second cell is in response to the current of the first electrical pulse satisfying the triggering threshold.
13. The method of claim 12 , further comprising terminating the first electrical pulse in response to detecting that the current of the first electrical pulse satisfies the triggering threshold.
14. The method of claim 11 , wherein the second write operation includes a RESET operation configured to put the second cell in a relatively high-resistance state, the method further comprising:
after applying the first electrical pulse to the first cell, determining that an amount of time elapsed since the first electrical pulse was instantiated satisfies a termination threshold, wherein the termination threshold includes an amount of time that it takes for a current of the first electrical pulse to decay to twenty percent of the maximum current of the second electrical pulse; and
terminating the first electrical pulse in response to detecting that the amount of time elapsed satisfies the termination threshold.
15. The method of claim 11 , wherein the second write operation includes a SET operation configured to put the second cell in a relatively low-resistance state, the method further comprising:
after applying the first electrical pulse to the first cell; determining that an amount of time elapsed since the first electrical pulse was instantiated satisfies a triggering threshold, wherein the triggering threshold includes an amount of time that it takes for a current of the first electrical pulse to decay to twenty percent of a peak current of the first electrical pulse; and
wherein the applying the second electrical pulse to the second cell is in response to the amount of time elapsed satisfying the triggering threshold.
16. The method of claim 11 , wherein the first write operation and the second write operation are from a plurality of write operations that are scheduled to be written to the NVM device, wherein the plurality of write operations include both SET operations configured to put respective cells in a relatively low-resistance state and RESET operations configured to put respective cells in a relatively high-resistance state, the method further comprising:
before applying the first electrical pulse to the first cell, reordering write operations of the plurality of write operations such that write operations that include SET operations configured to put respective cells into relatively low-resistance state are executed prior to write operations that include RESET operations configured to put respective cells into relatively high-resistance states.
17. The method of claim 11 , wherein the first cell and the second cell share either a bit line or a word line.
18. A system comprising:
means for receiving a plurality of write operations, wherein the plurality of write operations includes at least a first write operation and a second write operation, wherein the first write operation comprises a SET operation configured to place a cell of a NVM device in a relatively low-resistance state;
means for executing the first write operation by applying a first electrical pulse to a first cell to place the first cell of the NVM device in the relatively low-resistance state; and
means for executing the second write operation by applying a second electrical pulse to a second cell of the NVM device and to be overlapping with application of the first electrical pulse and before the first electrical pulse has concluded, wherein a single tile of the NVM device includes the first cell and the second cell.
19. The system of claim 18 , further comprising:
means for, when the second write operation includes a RESET operation, determining that a current of the first electrical pulse satisfies a first triggering threshold after applying the first electrical pulse to the first cell, wherein the first triggering threshold includes the current of the first electrical pulse decaying to a predetermined percent of the maximum current of the second electrical pulse, wherein the means for applying the second electrical pulse to the second cell applies the second electrical pulse in response to the current of the first electrical pulse satisfying the first triggering threshold; and
means for, when the second write operation includes a SET operation configured to put the second cell in a relatively low-resistance state, determining that a current of the first electrical pulse satisfies a second triggering threshold after applying the first electrical pulse to the first cell, wherein the second triggering threshold includes the current of the first electrical pulse decaying to twenty percent of a peak current of the first electrical pulse, wherein the means for applying the second electrical pulse to the second cell applies the second electrical pulse in response to the current of the first electrical pulse satisfying the second triggering threshold.
20. The system of claim 18 , wherein the first write operation and the second write operation are from a plurality of write operations that are scheduled to be written to the NVM device, wherein the plurality of write operations include both SET operations configured to put respective cells of the tile in a relatively low-resistance state and RESET operations configured to put respective cells of the tile in a relatively high-resistance state, the system further comprising:
means for reordering, before applying the first electrical pulse to the first cell, write operations of the plurality of write operations such that write operations that include SET operations configured to put respective cells into relatively low-resistance state are executed prior to write operations that include RESET operations configured to put respective cells into relatively high-resistance states.