Granted Patent B2

US 10,901,912 · App. 16/258,962 · Granted Jan 26, 2021

Inventors: Ramkumar Ramamurthy (Bangalore, IN); Ramanathan Muthiah (Bangalore, IN)

Assignee: Western Digital Technologies, Inc.

G06F12/1009G06F12/0246G06F2212/7201

Abstract

Claims (49)

1. Apparatus comprising:

a non-volatile memory; and

a memory controller coupled to the non-volatile memory, the memory controller configured to:

access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory;

receive a request from the host to write first data to the non-volatile memory, wherein the write request comprises a starting logical sector address;

determine that the first data comprises fragmented data that are not aligned to a starting sector of a minimum write unit of the non-volatile memory, wherein the minimum write unit comprises a plurality of sectors;

create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping of individual sectors for the first data; and

include an entry in the GAT that points to the unaligned GAT page.

2. The apparatus of claim 1 , wherein the unaligned GAT page comprises a plurality of entries, each entry comprising an amount of data smaller than an amount of data in the minimum write unit.

3. The apparatus of claim 1 , wherein the unaligned GAT page comprises a plurality of entries, each entry associated with a corresponding sector of the non-volatile memory.

4. The apparatus of claim 1 , wherein the memory controller is further configured to:

receive a request from the host to write second data to the non-volatile memory;

determine that the second data comprises fragmented data that are aligned to the minimum write unit of the non-volatile memory;

create an aligned GAT page, wherein the aligned GAT page comprises a logical-to-physical mapping for the second data; and

include an entry in the GAT that points to the aligned GAT page.

5. The apparatus of claim 4 , wherein the aligned GAT page comprises a plurality of entries, each entry comprising an amount of data equal to an amount of data in the minimum write unit.

6. The apparatus of claim 4 , wherein the aligned GAT page comprises a plurality of entries, each entry associated with a corresponding flash management unit of the non-volatile memory.

7. The apparatus of claim 1 , wherein the memory controller is further configured to:

receive a request from the host to write third data to the non-volatile memory;

determine that the third data comprises sequential data;

create an entry in the GAT that comprises a logical-to-physical mapping for the third data.

8. The apparatus of claim 7 , wherein the GAT comprises a plurality of entries comprising a logical group.

9. The apparatus of claim 7 , wherein the GAT comprises a plurality of entries comprising a plurality of logical groups.

10. The apparatus of claim 1 , wherein the GAT comprises a plurality of entries, each entry comprising a flag indicating whether data stored in physical addresses of the non-volatile memory comprise sequential data or fragmented data.

11. The apparatus of claim 1 , wherein the GAT comprises a plurality of entries, each entry comprising a flag indicating whether data stored in physical addresses of the non-volatile memory comprise data aligned to the minimum write unit of the non-volatile memory, or data unaligned to the minimum write unit of the non-volatile memory.

12. The apparatus of claim 1 , wherein the GAT comprises the unaligned GAT page.

13. The apparatus of claim 1 , wherein the GAT comprises the aligned GAT page.

14. A method comprising:

maintaining in a memory system a global address table (GAT) for mapping logical-to-physical address in a non-volatile memory;

receiving by the memory system from a host data to be written to the non-volatile memory, wherein the data to be written comprises a starting logical sector address;

determining that the data to be written is not aligned to a starting sector of a minimum write unit of the non-volatile memory, wherein the minimum write unit comprises a plurality of sectors;

indexing the data to be written in an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping of individual sectors of the data to be written; and

including an entry in the GAT that points to the unaligned GAT page.

15. The method of claim 14 , further comprising:

determining that the data to be written is aligned to a minimum write unit of the non-volatile memory; and

indexing the data to be written in an aligned GAT page.

16. The method of claim 14 , further comprising:

determining that the data to be written comprises sequential data; and

creating an entry in the GAT that comprises a logical-to-physical mapping for the data to be written.

17. The method of claim 14 , wherein the unaligned GAT page comprises a plurality of entries, each entry comprising an amount of data smaller than an amount of data in the minimum write unit.

18. The method of claim 15 , wherein the aligned GAT page comprises a plurality of entries, each entry comprising an amount of data equal to an amount of data in the minimum write unit.

19. The method of claim 16 , wherein the entry in the GAT comprises a plurality of entries comprising a logical group.

20. A memory system comprising:

a non-volatile memory comprising a plurality of memory cells;

a memory controller coupled to the non-volatile memory, the memory controller configured to:

receive a request from the host to write data to the non-volatile memory, wherein the write request comprises a starting logical sector address;

determine that the data comprises fragmented data that are not aligned to a starting sector of a minimum write unit of the non-volatile memory;

create entries in a logical-to-physical mapping table of individual sectors of the data, wherein a sector comprises less than a minimum write unit of the non-volatile memory; and

write the data to the non-volatile memory.

Assignments (10)