Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array
A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.
1. A storage system, comprising:
a decoder;
an encoder;
a memory configured to store first instruction code for implementing an additional decoder and second instruction code for implementing an additional encoder; and
a controller configured to:
execute the first instruction code in response to a first condition being satisfied; and
execute the second instruction code in response to a second condition being satisfied.
2. The storage system of claim 1 , wherein the first condition is satisfied during a read-intensive period, and wherein the second condition is satisfied during a write-intensive period.
3. The storage system of claim 1 , wherein the controller is further configured to:
track the read and write host requests or performance of the storage system; and
compare the tracked read and write host requests or performance of the storage system to a benchmark.
4. The storage system of claim 1 , wherein the first and second conditions relate to one or more of the following: type of application, type of configuration, type of virtual host, queue depth, a power condition, and a temperature condition.
5. The storage system of claim 1 , wherein the second condition is satisfied when the storage system is in burst mode.
6. The storage system of claim 5 , wherein the burst mode is detected using a predictable latency period configured by the host.
7. The storage system of claim 1 , wherein the controller comprises a field programmable gate array either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.
8. A storage system, comprising:
a decoder;
an encoder;
controller means;
a memory configured to store first instruction code for implementing an additional decoder and second instruction code for implementing an additional encoder;
means for programming the controller means with the first instruction code in response to a first condition being satisfied; and
means for programming the controller means with second instruction code in response to a second condition being satisfied.
9. The storage system of claim 8 , wherein the first condition is satisfied during a read-intensive period, and wherein the second condition is satisfied during a write-intensive period.
10. storage system of claim 8 , further comprising:
means for tracking the read and write host requests or performance of the storage system; and
means for comparing the tracked read and write host requests or performance of the storage system to a benchmark.
11. The storage system of claim 8 , wherein the first and second conditions relate to one or more of the following: type of application, type of configuration, type of virtual host, queue depth, a power condition, and a temperature condition.
12. The storage system of claim 8 , wherein the second condition is satisfied when the storage system is in burst mode.
13. The storage system of claim 12 , wherein the burst mode is detected using a predictable latency period configured by the host.
14. The storage system of claim 8 , wherein the controller means comprises a field programmable gate array either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.
15. In a storage system including a controller, a decoder, an encoder, a memory configured to store first instruction code for implementing an additional decoder and second instruction code for implementing an additional encoder, the method comprising:
programming the controller with the first instruction code in response to a first condition being satisfied; and
programming the controller with second instruction code in response to a second condition being satisfied.
16. The method of claim 15 , wherein the first condition is satisfied during a read-intensive period, and wherein the second condition is satisfied during a write-intensive period.
17. The method of claim 15 , further comprising:
tracking the read and write host requests or performance of the storage system; and
comparing the tracked read and write host requests or performance of the storage system to a benchmark.
18. The method of claim 15 , wherein the first and second conditions relate to one or more of the following: type of application, type of configuration, type of virtual host, queue depth, a power condition, and a temperature condition.
19. The method of claim 15 , wherein the second condition is satisfied when the storage system is in burst mode.
20. The method of claim 15 , wherein the controller comprises a field programmable gate array either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.