IP Library Granted Patent US 11,269,645
Granted Patent B2
US 11,269,645 · App. 16/815,860 · Granted Mar 8, 2022

Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array

Inventors: Ariel Navon (Revava, IL); Ran Zamir (Ramat Gan, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F9/3836G06F9/44505G06F11/076G06F11/0727
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Quick Facts
Patent No.
US 11,269,645
App. No.
16/815,860
Granted
Mar 8, 2022
Kind
B2
Abstract

A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.

Claims (33)

1. A storage system, comprising:

a memory configured to store a plurality of sets of instruction code, wherein each set is for a different error decoder implementation; and

a controller configured to:

select one of the sets of instruction code;

read the instruction code of the selected set from the memory; and

program the controller with the instruction code of the selected set, wherein the controller implements the error decoder specified in the instruction code of the selected set.

2. The storage system of claim 1 , wherein the selected set is selected based on a bit error rate or an estimation of the bit error rate.

3. The storage system of claim 1 , wherein the selected set is selected based on a program/erase count.

4. The storage system of claim 1 , wherein the selected set is selected based on a command from a host.

5. The storage system of claim 1 , wherein the controller comprises a field programmable gate array.

6. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

7. The storage system of claim 1 , wherein the controller is either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.

8. In a storage system including a controller and a memory configured to store a plurality of sets of instruction code, wherein each set is for a different error decoder implementation, a method comprising:

selecting one of the sets of instruction code;

reading the instruction code of the selected set from the memory; and

programing the controller with the instruction code of the selected set, wherein the controller implements the error decoder specified in the instruction code of the selected set.

9. The method of claim 8 , wherein the selected set is selected based on a bit error rate or an estimation of the bit error rate.

10. The method of claim 8 , wherein the selected set is selected based on a program/erase count.

11. The method of claim 8 , wherein the selected set is selected based on a command from a host.

12. The method of claim 8 , wherein the controller comprises a field programmable gate array.

13. The method of claim 8 , wherein the memory comprises a three-dimensional memory.

14. The method of claim 8 , wherein the controller is either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.

15. A storage system, comprising:

a memory configured to store a plurality of sets of instruction code, wherein each set is for a different error decoder implementation; and

a controller means for:

selecting one of the sets of instruction code;

reading the instruction code of the selected set from the memory; and

programing the controller means with the instruction code of the selected set, wherein the controller means implements the error decoder specified in the instruction code of the selected set.

16. The storage system of claim 15 , wherein the selected set is selected based on a bit error rate or an estimation of the bit error rate.

17. The storage system of claim 15 , wherein the selected set is selected based on a program/erase count.

18. The storage system of claim 15 , wherein the selected set is selected based on command from a host.

19. The storage system of claim 15 , wherein the controller means comprises a field programmable gate array.

20. The storage system of claim 15 , wherein the controller means is either programmed only once to support a specific product configuration or programmed a plurality of times throughout a lifetime of the storage system.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2020
From: NAVON, ARIEL; ZAMIR, RAN; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052088/0168 →
Continuity (1)
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