IP Library Granted Patent US 11,029,874
Granted Patent B2
US 11,029,874 · App. 16/526,866 · Granted Jun 8, 2021

Rolling XOR protection in efficient pipeline

Inventors: Yoav Markus (Tel-Aviv, IL); Alexander Bazarsky (Holon, IL); Alexander Kalmanovich (Jerusalem, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0647G06F3/0619G06F3/0652G06F3/0659G06F3/0673
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Quick Facts
Patent No.
US 11,029,874
App. No.
16/526,866
Granted
Jun 8, 2021
Kind
B2
Abstract

Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.

Claims (100)

1. A storage device controller comprising:

a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM); and

processing circuitry, configured to:

for each of the one or more SLs:

generate signature metadata; and

provide the signature metadata in a header of the SL;

XOR two or more SLs of the one or more SLs with their respective signature metadata to generate a signature; and

write the signature to the NVM, wherein the signature includes a signature portion and a metadata portion, the signature portion including an XOR of the two or more SLs, and the metadata portion including an XOR of the signature metadata of the two or more SLs.

2. The storage device controller of claim 1 , wherein the processing circuitry is further configured to write the one or more SLs to MLC NVM and the signature to SLC NVM.

3. The storage device controller of claim 2 , wherein the processing circuitry is further configured to:

determine that the one or more SLs have been safely written to the MLC NVM; and

delete the signature from the SLC NVM.

4. The storage device controller of claim 1 , wherein the metadata of the signature indicates each SL that is used to generate the signature portion.

5. The storage device controller of claim 4 , wherein the one or more SLs are to be each respectively programmed into a set of dies.

6. The storage device controller of claim 5 , wherein within the signature metadata for each SL a die to which a SL is to be programmed is indicated by a relative position of an identifier of the die within a pre-defined metadata field.

7. The storage device controller of claim 5 , wherein within the signature metadata for each SL a logical die to which a SL is to be programmed is indicated by a relative position of an identifier of the logical die within a pre-defined metadata field.

8. A storage device controller comprising:

a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM); and

processing circuitry, configured to:

for each of the one or more SLs:

generate signature metadata; and

provide the signature metadata in a header of the SL;

XOR two or more SLs of the one or more SLs with their respective signature metadata to generate a signature; and

write the signature to the NVM;

wherein the processing circuitry is further configured to, following power restoration after an ungraceful shut down (UGSD):

determine if at a time of the UGSD there was an ongoing write;

read a metadata portion of the last signature stored in SLC NVM; and

determine if any of the one or more SLs is absent from the signature.

9. The storage device controller of claim 8 , wherein the processing circuitry is further configured to, for each of the SLs absent from the signature:

XOR SLs missing from the last stored signature with the last stored signature to complete the signature; and

write the completed signature to SLC NVM.

10. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature, wherein the signature includes a signature portion and a metadata portion, the signature portion including an XOR of the set of SLs, and the metadata portion including an XOR of the signature metadata of the set of SLs; and

program both the updated signature and the signature metadata to a block of the SLC NVM.

11. The storage device of claim 10 , wherein the device controller further comprises random access memory (RAM), and wherein the RAM comprises the temporary storage.

12. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature; and

program both the updated signature and the signature metadata to a block of the SLC NVM, wherein if there is no previous version of signature metadata in the temporary storage, the processing circuitry is further configured to store the signature metadata for the current SL in the temporary storage.

13. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature; and

program both the updated signature and the signature metadata to a block of the SLC NVM, wherein if there is no previous version of the signature in the temporary storage, the processing circuitry is further configured to store the current SL in the temporary storage.

14. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature; and

program both the updated signature and the signature metadata to a block of the SLC NVM, wherein the set of SLs is to be programmed into a set of dies of the MLC, and wherein the signature metadata indicates a number N of the SLs is to be programmed into each die.

15. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature; and

program both the updated signature and the signature metadata to a block of the SLC NVM, wherein the signature metadata for the current SL indicates how many SLs, including the current SL, are included in the updated signature.

16. A storage device, comprising:

SLC non-volatile memory (NVM) and MLC NVM; and

a device controller, comprising:

a host interface, configured to receive a current string line (SL) of data from a host, the current SL one of a set of SLs to be programmed into dies of the MLC NVM; and

processing circuitry, configured to:

generate signature metadata for the current SL and store the metadata in temporary storage by overwriting a previously stored version of the signature metadata;

XOR the current SL with a previously stored version of a signature to generate an updated signature and store the updated signature in temporary storage by overwriting a previous version of the signature; and

program both the updated signature and the signature metadata to a block of the SLC NVM, wherein the signature metadata for the current SL indicates a location of a first protected die page.

17. An apparatus, comprising:

memory means;

means for receiving one or more string lines (SLs) of data from a host;

means for programming the one or more SLs to the memory means;

means for generating signature metadata for the one or more SLs, wherein a signature includes a signature portion and a metadata portion, the signature portion including an XOR of the one or more SLs, and the metadata portion including an XOR of the signature metadata of the one or more SLs;

means for XORing the one or more SLs with a previously stored signature metadata to generate an updated signature metadata; and

means for programming the updated signature metadata and the signature metadata to the memory means.

18. The apparatus of claim 17 , wherein the memory means comprises SLC non-volatile memory (NVM) and MLC NVM.

19. An apparatus, comprising:

memory means;

means for receiving one or more string lines (SLs) of data from a host;

means for programming the one or more SLs to the memory means;

means for generating signature metadata for the one or more SLs;

means for XORing the one or more SLs with a previously stored signature metadata to generate an updated signature metadata;

means for programming the updated signature metadata and the signature metadata to the memory means;

means for determining, following an ungraceful shut down (UGSD), whether a write process to a MLC NVM was ongoing;

means for reading metadata of a last written XOR signature to a SLC NVM, the XOR signature protecting data being written to the MLC NVM, wherein the means for reading metadata further comprises means for obtaining memory locations that were indicated as absent from the last XOR signature;

means for determining if the last written XOR signature is a partial signature;

means for completing the XOR signature; and

means for writing the completed XOR signature to SLC NVM.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2019
From: MARKUS, YOAV; BAZARSKY, ALEXANDER; KALMANOVICH, ALEXANDER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049934/0411 →
Continuity (1)
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