Nano-imprinted self-aligned multi-level processing method
View Patent ↗The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F 2 3D cross-point memory array has been formed.
1. A method comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
depositing a first plurality of layers in the first trench;
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
depositing a second plurality of layers in the second trench;
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate; and
depositing a third plurality of layers in the third trench, wherein the first portion has a first height, the second portion has a second height and the third portion has a third height, and wherein the second height is less than the first height and the third height is less than the second height.
2. A method comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
depositing a first plurality of layers in the first trench;
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
depositing a second plurality of layers in the second trench;
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate; and
depositing a third plurality of layers in the third trench, wherein the first planarized hard mask material covers the second portion and the third portion.
3. A method comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
depositing a first plurality of layers in the first trench;
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
depositing a second plurality of layers in the second trench;
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate; and
depositing a third plurality of layers in the third trench, wherein the second planarized hard mask material covers the first portion and the third portion.
4. A method comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
depositing a first plurality of layers in the first trench;
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
depositing a second plurality of layers in the second trench;
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate; and
depositing a third plurality of layers in the third trench, wherein the third planarized hard mask material covers the first portion and the second portion.
5. A method, comprising:
planarizing a hard mask material to expose a first portion of a substrate;
etching a first trench into the first portion of the substrate;
filling the first trench with a first metal material;
etching the first metal material to form a first layer of first metal material;
filling the first trench with a dielectric material;
etching the dielectric material;
filling the first trench with the first metal material;
etching the first metal material to form a second layer of first metal material;
filling the first trench with the dielectric material;
etching the dielectric material; and
filling the first trench with a first additional amount of hard mask material.
6. The method of claim 5 , further comprising:
planarizing the hard mask material to expose a second portion of the substrate;
etching a second trench into the second portion of the substrate;
filling the second trench with the first metal material;
etching the first metal material to form a third layer of first metal material.
7. The method of claim 6 , further comprising:
filling the second trench with a memory cell information storage material;
etching the memory cell information storage material to form a first layer of memory cell information storage material;
filling the second trench with an ovonic threshold switching material; and
etching the ovonic threshold switching material to form a first layer of ovonic threshold switching material.
8. The method of claim 7 , further comprising:
filling the second trench with a second metal material;
etching the second metal material to form a first layer of second metal material;
filling the trench with the dielectric material;
etching the dielectric material;
filling the second trench with the first metal material; and
etching the first metal material to form a fourth layer of first metal material.
9. The method of claim 8 , further comprising:
filling the second trench with the memory cell information storage material;
etching the memory cell information storage material to form a second layer of memory cell information storage material;
filling the second trench with the ovonic threshold switching material; and
etching the ovonic threshold switching material to form a second layer of ovonic threshold switching material.
10. The method of claim 9 , further comprising:
filling the second trench with the second metal material;
etching the second metal material to form a second layer of second metal material; and
filling the second trench with a second additional amount of hard mask material.
11. The method of claim 10 , further comprising:
planarizing the hard mask material to expose a third portion of the substrate;
etching a third trench into the third portion of the substrate;
filling the third trench with the second metal material; and
etching the second metal material to form a third layer of second metal material.
12. The method of claim 11 , wherein the second planarized hard mask material covers the first portion and the third portion.
13. The method of claim 11 , wherein the third planarized hard mask material covers the first portion and the second portion.
14. The method of claim 11 , further comprising:
filling the third trench with a dielectric material;
etching the dielectric material;
filling the third trench with the second metal material; and
etching the second metal material to form a fourth layer of second metal material.
15. The method of claim 11 , wherein the wherein the first portion has a first height, the second portion has a second height and the third portion has a third height, and wherein the second height is less than the first height and the third height is less than the second height.
16. The method of claim 11 , wherein the first planarized hard mask material covers the second portion and the third portion.