MRAM array and access method thereof
View Patent ↗A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, memory elements, respectively, including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through the bitline, and a read wordline driver connected to the memory array adapted to provide a first read signal to a first read wordline of a plurality of read wordlines, wherein a second read signal is provided to activate a second read wordline while the first read wordline remains activated.
1. An access method for accessing a memory circuit block comprising a memory array in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, said respective wordlines consisting of read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, each of said memory element including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through respective bitline; a read wordline driver for providing a read signal to said read wordline; and a read circuit for providing a bitline read signal to said bitline, said access method comprising the steps of:
providing a first read signal onto a first read wordline to activate said first read wordline;
providing said bitline read signal to a first bitline; and
thereafter providing a second read signal onto a second read wordline while said first read signal is falling.
2. The memory circuit block access method according to claim 1 , further comprising reading data from a first memory element at the intersection of said first read wordline and said first bitline.
3. The memory circuit block access method according to claim 1 , further comprising providing a bitline read signal to a second bitline when providing said second read signal to said second read wordline.
4. The memory circuit block access method according to claim 3 further comprising, after providing said bitline read signal to said second bitline, reading data from a second memory element at the intersection of said second read wordline and said second bitline.
5. A magnetic random access memory (MRAM) array circuit block, comprising:
a memory array in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, said respective wordlines comprising read wordlines and write wordlines, respectively, and memory elements provided at intersections of said wordlines and said bitlines, each said memory element including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through a respective bitline coupled to said memory element;
a read wordline driver adapted to provide a read signal onto a first read wordline and adapted to provide a read signal onto a second read wordline while said first read signal is active; and
a read circuit for providing a bitline read signal to said bitline.
6. The memory circuit block according to claim 5 , wherein said read circuit is adapted to provide said bitline read signal to a predetermined bitline while said read signal is provided sequentially to respective ones of said plurality of read wordlines.
7. The memory circuit block according to claim 6 , wherein said memory element comprises an MTJ (Magnetic Tunnel Junction) element or a GMR (giant magnetoresistive) element.