IP Library › Granted Patent US 12,579,086
Granted Patent B2
US 12,579,086 · App. 18/351,363 · Granted Mar 17, 2026

Data storage with low cost dies

Inventor: Refael Ben-Rubi (Rosh Haayln, IL)
Assignee: Sandisk Technologies, Inc.
G06F13/1689G06F9/30189G06F13/1621
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,579,086
App. No.
18/351,363
Filed
Jul 12, 2023
Granted
Mar 17, 2026
Kind
B2
Art Unit
2137
USPC
711/154
Abstract

The present disclosure generally relates to improved command processing by separating all state machines into multiple groups. Rather than having one general die that can process any command, this disclosure suggests distributed processing commands by having two types of dies. A slave die will contain the flash array and implementation of state machine that is related to fast operations, and will not include state machines of slow operations. A master die will contain implementation of fast state machine (to support fast commands to the flash array that connected to the master die) and implementation of slow command state machine. The master die will have one instance of the slow state machine implementation, but that slow state machine will be able to be loaded with variables that represent the slow states of all the other dies. The commands processing is based the most suitable state machine for the specific command.

Claims (43)

1 . A data storage device, comprising:

a memory device, wherein the memory device comprises a master die and one or more slave dies, and wherein the master die is configured to direct non-real time operations to the one or more slave dies; and

a controller coupled to the memory device, wherein the controller is configured to:

direct real-time operations to the one or more slave dies; and

direct the real and non-real time operations to the master die, wherein real-time operations are selected from the group consisting of: read transfer state machine operations, bit XOR operations, and combinations thereof.

2 . The data storage device of claim 1 , wherein the master die is coupled to the one or more slave dies.

3 . The data storage device of claim 1 , wherein the master die includes RAM.

4 . The data storage device of claim 1 , wherein the master die is configured to:

load variables into a state machine, wherein the state machine is within the master die;

process the variables to generate an output; and

send the output to the one or more slave dies.

5 . The data storage device of claim 1 , wherein the master die is configured to activate the one or more slave dies.

6 . The data storage device of claim 1 , wherein the one or more slave dies are configured to report completion of the non-real time operations to the master die.

7 . The data storage device of claim 6 , wherein the master die is configured to report completion of the non-real time operations to the controller.

8 . A data storage device, comprising:

a memory device, wherein the memory device comprises a master die and one or more slave dies, and wherein the master die is configured to direct non-real time operations to the one or more slave dies; and

a controller coupled to the memory device, wherein the controller is configured to:

direct real-time operations to the one or more slave dies; and

direct the real and non-real time operations to the master die, wherein non-real time operations are selected from the group consisting of: read temperature state machine operations, operations that are not parallel processed, and combinations thereof.

9 . The data storage device of claim 8 , wherein the one or more slave dies are configured to report completion of the real-time operations to the controller.

10 . The data storage device of claim 8 , wherein the master die will receive the real-time operations for synchronization purposes.

11 . The data storage device of claim 8 , wherein the controller comprises a plurality of flash interface modules (FIMs) and wherein each FIM of the plurality of FIMs is coupled to the master die.

12 . A data storage device, comprising:

a memory device comprising a plurality of dies; and

a controller coupled to the memory device, the controller comprising:

one or more flash interface modules (FIMs) coupled to the plurality of dies; and

a slow state machine controller coupled to the one or more FIMs, wherein the controller is configured to:

send real-time operations through the one or more FIMs to one of more dies of the plurality of dies, wherein real-time operations are selected from the group consisting of: read transfer state machine operations, bit XOR operations, and combinations thereof; and

send state machine output to the one or more dies for non-real time operations, wherein non-real time operations are selected from the group consisting of: read temperature state machine operations, operations that are not parallel processed, and combinations thereof.

13 . The data storage device of claim 12 , wherein the slow state machine controller sends the state machine output through the one or more FIMs to the one or more dies of the plurality of dies.

14 . The data storage device of claim 12 , wherein the one or more dies do not include state machines for non-real time operations.

15 . The data storage device of claim 12 , wherein the one or more dies are configured to report completion of the real-time operations to the controller using a ready/busy signal or sending register data that was read to the controller.

16 . The data storage device of claim 12 , wherein the slow state machine controller is configured to process variables for non-real time operations in a state machine to generate the state machine output.

17 . A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller includes a plurality of flash interface modules (FIMs), and wherein the controller is configured to:

direct real-time operations to a first location of the memory means, wherein real-time operations are selected from the group consisting of: read transfer state machine operations, bit XOR operations, and combinations thereof;

direct parallel processing operations to the first location of the memory means;

direct non-real time operations to one or more second locations of the memory means, wherein non-real time operations are selected from the group consisting of: read temperature state machine operations, operations that are not parallel processed, and combinations thereof; and

direct operations that do not require parallel processing to the one or more second locations of the memory means, wherein the one or more second locations of the memory means are configured to send output information from a state machine to the first location of the memory means.

18 . The data storage device of claim 17 , wherein a first FIM of the plurality of FIMs is coupled to the first location and at least a location of the one or more second locations.

19 . The data storage device of claim 18 , wherein a second FIM of the plurality of FIMs is coupled to other locations of the one or more second locations, wherein the other location of the one or more second locations is distinct from the location of the one or more second locations.

20 . The data storage device of claim 17 , wherein the data storage device does not include dynamic random access memory (DRAM).

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: BEN-RUBI, REFAEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064655/0289 →
Continuity (2)
Provisional Application 63415167 · Oct 11, 2022
Related Publication 20240119016A1 · Apr 11, 2024
References Cited (8)
US 8058897B1 · Lu et al. · 2011 [cited by applicant]
US 10642513B2 · Marcu et al. · 2020 [cited by applicant]
US 11226767B1 · Johnson et al. · 2022 [cited by applicant]
US 11256591B2 · Alrod et al. · 2022 [cited by applicant]
US 20160313914A1 · Koets · 2016 [cited by examiner]
US 20180173659A1 · DenBoer · 2018 [cited by examiner]
US 20210157519A1 · Dash · 2021 [cited by examiner]
Jung, Myoungsoo et al. “NANDFlashSim: High-Fidelity, Microarchitecture-Aware NAND Flash Memory Simulation” vol. 12, No. 2, Article 6, Publication: Jan. 2016. [cited by applicant]