Non-volatile semiconductor memory segregating sequential, random, and system data to reduce garbage collection for page based mapping
View Patent ↗A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones.
1. A non-volatile semiconductor memory comprising:
a memory device comprising a memory array including a plurality of memory segments; and
control circuitry operable to:
allocate a first set of the plurality of memory segments to a first zone and a second set of the plurality of memory segments to a second zone, wherein the first zone is reserved for storing sequential data and the second zone is reserved for storing random data;
receive a plurality of sequential access write commands including sequential data from a host after said allocation of memory segments to the first zone, wherein each of the sequential access write commands identifies one or more logical block addresses (LBAs);
receive a plurality of random access write commands including random data from the host after said allocation of memory segments to the second zone, wherein each of the random access write commands identifies one or more LBAs;
map the LBAs identified by the sequential access write commands to one or more memory segments of the first zone to generate sequential mapping data including zone number and page number information associated with the one or more memory segments of the first zone;
store the sequential data in the one or more memory segments of the first zone;
allocate a third set of the plurality of memory segments to a third zone for storing sequential mapping data and store the sequential mapping data in the third zone;
map the LBAs identified by the random access write commands to one or more memory segments of the second zone to generate random mapping data including zone number and page number information associated with the one or more memory segments of the second zone;
store the random data in the one or more memory segments of the second zone; and
allocate a fourth set of the plurality of memory segments to a fourth zone for storing random mapping data and store the random mapping data in the fourth zone.
2. The non-volatile semiconductor memory as recited in claim 1 , wherein the control circuitry is further operable to:
allocate a fifth set of the plurality of memory segments to a fifth zone for storing system data;
generate a plurality of system access write commands to write system data to the memory device, wherein each system access write command identifies one or more LBAs;
map the LBAs identified by the system access write commands to one or more memory segments of the fifth zone to generate system mapping data.
3. The non-volatile semiconductor memory as recited in claim 2 , wherein:
the plurality of memory segments comprises a plurality of blocks, each block comprising a plurality of pages;
the control circuitry is further operable to erase a page by erasing an entire block;
the first zone comprises a first block;
the second zone comprises a second block; and
the third zone comprises a third block.
4. The non-volatile semiconductor memory as recited in claim 2 , wherein the control circuitry is further operable to:
allocate a sixth set of the plurality of memory segments to a sixth zone for storing system mapping data and store the system mapping data in the sixth zone after executing the plurality of the system access write commands.
5. The non-volatile semiconductor memory as recited in claim 4 , wherein the control circuitry is further operable to erase a block in one of the first, second, third, fourth, fifth or sixth zones without relocating valid pages from the block to another block.
6. A method of operating a non-volatile semiconductor memory comprising a memory device comprising a memory array including a plurality of memory segments, the method comprising:
allocating a first set of the plurality of memory segments to a first zone and a second set of the plurality of memory segments to a second zone, wherein the first zone is reserved for storing sequential data and the second zone is reserved for storing random data;
receiving a plurality of sequential access write commands including sequential data from a host after said allocating memory segments to the first zone, wherein each of the sequential access write commands identifies one or more logical block addresses (LBAs);
receiving a plurality of random access write commands including random data from the host after said allocating memory segments to the second zone, wherein each of the random access write commands identifies one or more LBAs;
mapping the LBAs identified by the sequential access write commands to one or more memory segments of the first zone to generate sequential mapping data including zone number and page number information associated with the one or more memory segments of the first zone;
storing the sequential data in the one or more memory segments of the first zone;
allocating a third set of the plurality of memory segments to a third zone for storing sequential mapping data and storing the sequential mapping data in the third zone;
mapping the LBAs identified by the random access write commands to one or more memory segments of the second zone to generate random mapping data including zone number and page number information associated with the one or more memory segments of the second zone;
storing the random data in the one or more memory segments of the second zone; and
allocating a fourth set of the plurality of memory segments to a fourth zone for storing random mapping data and storing the random mapping data in the fourth zone.
7. The method as recited in claim 6 , further comprising:
allocating a fifth set of the plurality of memory segments to a fifth zone for storing system mapping data;
generating a plurality of system access write commands to write system data to the memory device, wherein each system access write command identifies one or more LBAs;
mapping the LBAs identified by the system access write commands to one or more memory segments of the fifth zone to generate system mapping data.
8. The method as recited in claim 7 , wherein:
the plurality of memory segments comprise a plurality of blocks, each block comprising a plurality of pages;
a page is erased by erasing an entire block;
the first zone comprises a first block;
the second zone comprises a second block; and
the third zone comprises a third block.
9. The method as recited in claim 7 , further comprising:
allocating a sixth set of the plurality of memory segments to a sixth zone for storing system mapping data and storing the system mapping data in the sixth zone after executing the plurality of the system access write commands.
10. The method as recited in claim 9 , further comprising erasing a block in one of the first, second, third, fourth, fifth or sixth zones without relocating valid pages from the block to another block.