IP Library Granted Patent US 10,360,155
Granted Patent B1
US 10,360,155 · App. 15/946,387 · Granted Jul 23, 2019

Multi-tier memory management

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,360,155
App. No.
15/946,387
Granted
Jul 23, 2019
Kind
B1
Abstract

The disclosure relates in some aspects to managing multi-tier memory, such as multi-tier NVM. Data that is originally written to a first tier (e.g., a fast tier) may be subsequently copied to a second tier (e.g., a slow tier). The data is temporarily left in the first tier until the space is needed for a subsequent write operation. Thus, for a period of time, a read operation is able to read the data from the first tier (e.g., the fast tier) instead of the second tier (e.g., the slow tier), thereby improving read performance. The disclosure relates in some aspects to a memory mapping scheme that enables a read operation to readily determine that data remains in the first tier and locate the data in that tier. Moreover, the scheme enables efficient reconfiguration of the mapping when the data in the first tier is erased.

Claims (83)

1. A data storage method, comprising:

copying data from a block of a first type of non-volatile memory to a block of a second type of non-volatile memory, wherein a cell of the second type of non-volatile memory is configured to store more information than a cell of the first type of non-volatile memory;

modifying a first memory map to include a mapping of a logical block address to the block of the second type of non-volatile memory;

modifying a second memory map to include a mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory; and

setting an indication to indicate that the data remains in the block of the first type of non-volatile memory.

2. The method of claim 1 , further comprising:

receiving a read command comprising the logical block address;

determining, in response to the receipt of the read command, that the indication is set;

determining a location of the data in the block of the first type of non-volatile memory based on the second memory map as a result of the determination that the indication is set; and

reading the data from the determined location in the block of the first type of non-volatile memory.

3. The method of claim 2 , further comprising:

identifying the block of the second type of non-volatile memory for the read command based on the logical block address and the first memory map,

wherein the determination of the location is based on the identified block of the second type of non-volatile memory.

4. The method of claim 1 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory maps an offset of the copied data into the block of the second type of non-volatile memory to an offset of the data into the block of the first type of non-volatile memory.

5. The method of claim 1 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory comprises a table including:

an identifier of the block of the first type of non-volatile memory; and

an offset at which the data was copied into the block of the second type of non-volatile memory.

6. The method of claim 5 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory further comprises:

an offset of the data into the block of the first type of non-volatile memory.

7. The method of claim 6 , further comprising determining a location of the data in the block of the first type of non-volatile memory in response to a read command by:

determining a location of the offset of the data into the block of the first type of non-volatile memory based on the identifier of the block of the first type of non-volatile memory and the offset at which the data was copied into the block of the second type of non-volatile memory.

8. The method of claim 5 , further comprising determining a location of the data in the block of the first type of non-volatile memory in response to a read command by:

determining that the read command is directed to a particular block of the second type of non-volatile memory and to a particular offset within the particular block; and

identifying an entry of the table based on the particular block and the particular offset.

9. The method of claim 8 , wherein the determination that the read command is directed to the particular block of the second type of non-volatile memory is based on the first memory map.

10. The method of claim 1 , wherein the copying of the data comprises:

identifying valid data in the block of the first type of non-volatile memory; and

storing the valid data at a range of offsets in the block of the second type of non-volatile memory.

11. The method of claim 1 , further comprising:

modifying a third memory map to include a mapping from the block of the first type of non-volatile memory to the block of the second type of non-volatile memory.

12. The method of claim 11 , further comprising:

determining that the block of the first type of non-volatile memory is to be erased;

determining a location of the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory in the second memory map in response to the determination that the block of the first type of non-volatile memory is to be erased, wherein the determination of the location is based on the third memory map;

modifying the second memory map at the determined location to delete at least a portion of the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory; and

erasing the block of the first type of non-volatile memory.

13. The method of claim 1 , wherein:

the first memory map maps logical blocks of a first block size to physical blocks of the first block size; and

the first block size is smaller than a block size of the block of the second type of non-volatile memory.

14. The method of claim 1 , wherein an access time for the first type of non-volatile memory is faster than an access time for the second type of non-volatile memory.

15. The method of claim 1 , wherein the first memory map and the second memory map are modified as a result of the copying.

16. An apparatus for controlling data storage, comprising:

a first type of non-volatile memory;

a second type of non-volatile memory; and

a processor coupled to the first type of non-volatile memory and the second type of non-volatile memory and configured to:

copy data from a block of a first type of non-volatile memory to a block of a second type of non-volatile memory, wherein a cell of the second type of non-volatile memory is configured to store more information than a cell of the first type of non-volatile memory,

modify a first memory map to include a mapping of a logical block address to the block of the second type of non-volatile memory,

modify a second memory map to include a mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory, and

set an indication to indicate that the data remains in the block of the first type of non-volatile memory.

17. The apparatus of claim 16 , wherein the processor is further configured to:

receive a read command comprising the logical block address;

determine, in response to the receipt of the read command, that the indication is set;

determine a location of the data in the block of the first type of non-volatile memory based on the second memory map as a result of the determination that the indication is set; and

read the data from the determined location in the block of the first type of non-volatile memory.

18. The apparatus of claim 17 , wherein:

the processor is further configured to identify the block of the second type of non-volatile memory for the read command based on the logical block address and the first memory map; and

the determination of the location is based on the identified block of the second type of non-volatile memory.

19. The apparatus of claim 16 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory maps an offset of the copied data into the block of the second type of non-volatile memory to an offset of the data into the block of the first type of non-volatile memory.

20. The apparatus of claim 16 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory comprises a table including:

an identifier of the block of the first type of non-volatile memory; and

an offset at which the data was copied into the block of the second type of non-volatile memory.

21. The apparatus of claim 20 , wherein the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory further comprises:

an offset of the data into the block of the first type of non-volatile memory.

22. The apparatus of claim 21 , wherein the processor is further configured to determine a location of the data in the block of the first type of non-volatile memory in response to a read command by:

determining a location of the offset of the data into the block of the first type of non-volatile memory based on the identifier of the block of the first type of non-volatile memory and the offset at which the data was copied into the block of the second type of non-volatile memory.

23. The apparatus of claim 20 , wherein the processor is further configured to determine a location of the data in the block of the first type of non-volatile memory in response to a read command by:

determining that the read command is directed to a particular block of the second type of non-volatile memory and to a particular offset within the particular block; and

identifying an entry of the table based on the particular block and the particular offset.

24. The apparatus of claim 23 , wherein the determination that the read command is directed to the particular block of the second type of non-volatile memory is based on the first memory map.

25. The apparatus of claim 16 , wherein the copying of the data comprises:

identifying valid data in the block of the first type of non-volatile memory; and

storing the valid data at a range of offsets in the block of the second type of non-volatile memory.

26. The apparatus of claim 16 , wherein the processor is further configured to:

modify a third memory map to include a mapping from the block of the first type of non-volatile memory to the block of the second type of non-volatile memory.

27. The apparatus of claim 26 , wherein the processor is further configured to:

determine that the block of the first type of non-volatile memory is to be erased;

determine a location of the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory in the second memory map in response to the determination that the block of the first type of non-volatile memory is to be erased, wherein the determination of the location is based on the third memory map;

modify the second memory map at the determined location to delete at least a portion of the mapping of the block of the second type of non-volatile memory to the block of the first type of non-volatile memory; and

erase the block of the first type of non-volatile memory.

28. The apparatus of claim 16 , wherein:

the first memory map maps logical blocks of a first block size to physical blocks of the first block size; and

the first block size is smaller than a block size of the block of the second type of non-volatile memory.

29. The apparatus of claim 16 , wherein an access time for the first type of non-volatile memory is faster than an access time for the second type of non-volatile memory.

30. The apparatus of claim 16 , wherein the first memory map and the second memory map are modified as a result of the copying.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2018
From: THOMAS, NICHOLAS JAMES; DAVIDSON, MATTHEW; EREZ, ERAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045453/0302 →