Optimized threshold translation from serialized pipeline
Aspects of a storage device are provided that simplify the encoding or translation of optimized read voltage thresholds into a given NAND register format, which may vary depending on NAND technology, block type, page type, or gray code layout. The storage device may include a memory, a circuit that is configured to shift and combine read threshold voltage offsets into a joint read voltage threshold offset, and a controller configured to store the joint read voltage threshold offset in the memory. The circuit may be implemented in hardware of the controller. Alternatively, the controller software or firmware itself may shift and combine the read threshold voltage offsets into the joint read voltage threshold offset. As a result, the number of instructions that the controller typically performs in translating the optimized thresholds may be reduced. Moreover, the simplified translation may be scalable to different NAND technologies or page types.
1. A storage device, comprising:
a memory;
a circuit configured to shift and combine read threshold voltage offsets corresponding to optimized read voltage thresholds into a joint read voltage threshold offset; and
a controller configured to store the joint read voltage threshold offset in the memory.
2. The storage device of claim 1 , wherein the memory includes a read voltage threshold register, and the controller is configured to store the joint read voltage threshold offset in the read voltage threshold register.
3. The storage device of claim 2 , wherein the read threshold voltage offsets are associated with inconsecutive memory locations of the read voltage threshold register.
4. The storage device of claim 1 , wherein the controller is further configured to configure a data structure in the memory including a shift value for each of the read threshold voltage offsets, and wherein the circuit is configured to shift the read threshold voltage offsets according to the shift values.
5. The storage device of claim 4 , wherein the data structure further includes a threshold count associated with the shift values, and wherein a number of the read threshold voltage offsets in the joint read voltage threshold offset is equivalent to the threshold count.
6. The storage device of claim 4 , wherein each of the shift values in the data structure is associated with a page type.
7. A storage device, comprising:
a memory; and
a controller configured to:
configure a data structure in the memory including a shift value for each of a plurality of read threshold voltage offsets,
shift the read threshold voltage offsets according to the shift values,
combine the shifted read threshold voltage offsets into a joint read voltage threshold offset, and
store the joint read voltage threshold offset in the memory.
8. The storage device of claim 7 , wherein the memory includes a plurality of read voltage threshold registers, and the controller is configured to store the joint read voltage threshold offset in one of the read voltage threshold registers.
9. The storage device of claim 8 , wherein the read threshold voltage offsets are associated with inconsecutive memory locations of the one of the read voltage threshold registers.
10. The storage device of claim 7 , wherein the shift values and a number of the read threshold voltage offsets are based on a block type, a page type, or a gray code layout of the storage device.
11. The storage device of claim 10 , wherein the controller is further configured to configure a threshold count associated with the shift values in the data structure, and wherein the number of the read threshold voltage offsets in the joint read voltage threshold offset is equivalent to the threshold count.
12. The storage device of claim 10 , wherein the data structure includes a page index associated with the shift values, the page index corresponding to the page type.
13. A storage device, comprising:
a memory including a read voltage threshold register;
means for shifting and combining read threshold voltage offsets into a joint read voltage threshold offset, the read threshold voltage offsets being shifted by different numbers of bits to align with respective memory locations of the read voltage threshold register; and
a controller configured to store the joint read voltage threshold offset in the memory.
14. The storage device of claim 13 , wherein the means for shifting and combining comprises a circuit.
15. The storage device of claim 13 , wherein the means for shifting and combining comprises a shifting and combining module of the controller.
16. The storage device of claim 13 , wherein the memory includes multiple read voltage threshold registers including the read voltage threshold register, and the controller is configured to store the joint read voltage threshold offset in the read voltage threshold register.
17. The storage device of claim 16 , wherein the read threshold voltage offsets are associated with discontinuous memory locations of the read voltage threshold register.
18. The storage device of claim 13 , wherein the controller is further configured to configure a data structure in the memory including a shift value for each of the read threshold voltage offsets, and the means for shifting and combining is configured to shift the read threshold voltage offsets according to the shift values.
19. The storage device of claim 18 , wherein the data structure further includes a number of thresholds associated with the shift values, and wherein a number of the read threshold voltage offsets in the joint read voltage threshold offset is equivalent to the number of thresholds.
20. The storage device of claim 18 , wherein the data structure includes a page index associated with each of the shift values, the page index being associated with a page type.