Neighbor plane disturb (NPD) detection for memory devices

1 . A memory device, comprising:

a plurality of memory cells arranged in a plurality of planes; and

control circuitry configured to perform a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein, to perform the multi-plane programming operation, the control circuitry is configured to

detect a neighbor plane disturb (NPD) defect during the multi-plane programming operation based on a program voltage applied to a word line of the memory device,

in response to detecting the NPD defect, terminate the multi-plane programming operation prior to completing the multi-plane programming operation, and

identify which plane of the plurality of planes includes the NPD defect.

2 . The memory device of claim 1 , wherein the control circuitry is configured to detect the NPD defect based on a determination of whether the program voltage reaches a target voltage level within a predetermined period.

3 . The memory device of claim 1 , wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes.

4 . The memory device of claim 1 , wherein, in response to detecting the NPD defect, the control circuitry is configured terminate the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation.

5 . The memory device of claim 1 , wherein, to identify which plane of the plurality of planes includes the NPD defect, the control circuitry is configured to (i) transition from a multi-plane programming mode to a single plane programming mode and (ii) sequentially perform single plane programming operations on each of the plurality of planes.

6 . The memory device of claim 5 , wherein, during the single plane programming operations, the control circuitry is configured to identify whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device.

7 . A method for operating a memory device including a plurality of memory cells arranged in a plurality of planes, the method comprising:

performing a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein performing the multi-plane programming operation includes

detecting a neighbor plane disturb (NPD) defect during the multi-plane programming operation based on a program voltage applied to a word line of the memory device,

in response to detecting the NPD defect, terminating the multi-plane programming operation prior to completing the multi-plane programming operation, and

identifying which plane of the plurality of planes includes the NPD defect.

8 . The method of claim 7 , further comprising detecting the NPD defect based on a determination of whether the program voltage reaches a target voltage level within a predetermined period.

9 . The method of claim 7 , wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes.

10 . The method of claim 7 , further comprising, in response to detecting the NPD defect, terminating the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation.

11 . The method of claim 7 , wherein identifying which plane of the plurality of planes includes the NPD defect includes (i) transitioning from a multi-plane programming mode to a single plane programming mode and (ii) sequentially performing single plane programming operations on each of the plurality of planes.

12 . The method of claim 11 , further comprising, during the single plane programming operations, identifying whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device.

13 . A memory device, comprising:

a plurality of memory cells arranged in a plurality of planes; and

control means for performing a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation, wherein, to perform the multi-plane programming operation, the control means

detects a neighbor plane disturb (NPD) defect during the multi-plane programming operation based on whether a program voltage applied to a word line of the memory device reaches a target voltage level within a predetermined time,

in response to detecting the NPD defect, terminates the multi-plane programming operation prior to completing the multi-plane programming operation, and

identifies which plane of the plurality of planes includes the NPD defect.

14 . The memory device of claim 13 , wherein the word line corresponds to a word line coupled to the memory cells in each of the plurality of planes.

15 . The memory device of claim 13 , wherein, in response to detecting the NPD defect, the control means terminates the multi-plane programming operation prior to completing a maximum number of programming loops associated with the multi-plane programming operation.

16 . The memory device of claim 13 , wherein, to identify which plane of the plurality of planes includes the NPD defect, the control means (i) transitions from a multi-plane programming mode to a single plane programming mode and (ii) sequentially performs single plane programming operations on each of the plurality of planes.

17 . The memory device of claim 16 , wherein, during the single plane programming operations, the control means identifies whether a selected plane has the NPD defect based on a program voltage applied to a word line of the memory device.