IP Library Granted Patent US 11,809,747
Granted Patent B2
US 11,809,747 · App. 17/558,089 · Granted Nov 7, 2023

Storage system and method for optimizing write-amplification factor, endurance, and latency during a defragmentation operation

Inventors: Einav Zilberstein (Had Hasharon, IL); Hadas Oshinsky (Kfar Saba, IL); Oren Ben Hayun (Petah Tikva, IL); Rotem Sela (Haifa, IL); Alex Lemberg (Kfar Saba, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/064G06F3/0619G06F3/0673
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Quick Facts
Patent No.
US 11,809,747
App. No.
17/558,089
Granted
Nov 7, 2023
Kind
B2
Abstract

A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.

Claims (38)

1. A storage system comprising:

a memory; and

a controller coupled to the memory and configured to:

dynamically determine a size of a defragmentation unit based on an endurance of the memory;

dynamically determine a memory sense threshold based on the endurance of the memory;

analyze a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and

for each defragmentation unit:

determine a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;

determine if the fragmentation level is above a fragmentation threshold; and

in response to determining that the fragmentation level is above the defragmentation threshold, perform a defragmentation operation on the defragmentation unit.

2. The storage system of claim 1 , wherein a size of the defragmentation unit decreases with an age of the storage system.

3. The storage system of claim 1 , wherein the defragmentation unit with no fragmentation is readable by a single memory sense.

4. The storage system of claim 1 , wherein the controller is further configured to dynamically define the threshold based on endurance and performance tradeoffs.

5. The storage system of claim 1 , wherein the controller is further configured to perform the defragmentation operation independent of receiving a read command from a host.

6. The storage system of claim 1 , wherein the controller is further configured to perform the defragmentation operation without receiving an instruction from a host to perform the defragmentation operation.

7. The storage system of claim 1 , wherein the data comprises a file.

8. The storage system of claim 1 , wherein the controller is further configured to identify the logical block address range.

9. The storage system of claim 1 , wherein the logical block address range is identified by a host.

10. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

11. A method performed in a storage system comprising a memory, the method comprising:

dynamically determining a size of a defragmentation unit based on an endurance of the memory;

dynamically determining a memory sense threshold based on the endurance of the memory;

analyzing a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and

for each defragmentation unit:

determining a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;

determining if the fragmentation level is above a fragmentation threshold; and

in response to determining that the fragmentation level is above the defragmentation threshold, performing a defragmentation operation on the defragmentation unit.

12. The method of claim 11 , wherein the defragmentation unit with no fragmentation is readable by a single memory sense.

13. The method of claim 11 , wherein the data comprises a file.

14. A storage system comprising:

a memory;

means for dynamically determining a size of a defragmentation unit based on an endurance of the memory;

means for dynamically determining a memory sense threshold based on the endurance of the memory;

means for analyzing a logical block address range of data stored in the memory, wherein the logical block address range is analyzed in a resolution of the defragmentation unit; and

means for, for each defragmentation unit:

determining a fragmentation level of the defragmentation unit by measuring a number of memory senses needed to read the defragmentation unit using the dynamically determined memory sense threshold;

determining if the fragmentation level is above a fragmentation threshold; and

in response to determining that the fragmentation level is above the defragmentation threshold, performing a defragmentation operation on the defragmentation unit.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2021
From: ZILBERSTEIN, EINAV; OSHINSKY, HADAS; HAYUN, OREN BEN; SELA, ROTEM; LEMBERG, ALEX
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058450/0388 →
Continuity (1)
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