Dynamic controller buffer management and configuration
A method and apparatus for dynamic controller buffer management is disclosed. According to certain embodiments, responsive to commands received from a host, a controller may adjust one or more partitions of a controller buffer memory to adjust the size of different types of buffer memory. In some embodiments, preset buffer memory configurations may be applied to the buffer memory to adjust buffer memory allocation based on the current workload. By way of example, when sequential reads are detected, a TRAM buffer size may be increased to provide additional RLA buffers, at the expense of XRAM and/or L2P buffer size. Where operations involving SLC memory is detected, allocation of buffer memory parity buffers of XRAM may be decreased, to provide additional buffer space to L2P.
1. A data storage device, comprising:
a non-volatile memory (NVM) device; and
a controller coupled to the NVM device, the controller comprising:
a buffer memory device comprising a first buffer partition, the first buffer partition being of a first buffer size, and a second buffer partition that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, wherein the first buffer partition comprises one of a transactional random access memory (TRAM) buffer, a logical to physical cache (L2P) buffer, or a parity random access memory (XRAM) buffer, wherein the second buffer partition comprises one of a TRAM buffer, an L2P buffer, or an XRAM buffer that is different from the first buffer partition, wherein the buffer memory device is a contiguous physical memory space, wherein a TRAM buffer is a holding buffer for write operations and relocation operations, wherein an L2P buffer is buffer space for storing parts of a logical to physical table mapping logical location references to physical locations on the NVM device, and wherein an XRAM buffer is configured to hold parity data accumulated for different pages of each open block of the NVM device; and
a processor coupled to the buffer memory device, the processor configured to:
identify a workload characteristic of a workload of the data storage device;
modify the first buffer size based on the workload characteristic; and
modify the second buffer size based on the modification of the first buffer size.
2. The data storage device of claim 1 , wherein the buffer memory further comprises a third buffer partition, that is different than the first buffer partition and second buffer partition, the third buffer partition being of a third buffer size, and wherein the processor is further configured to modify the third buffer size based on the workload characteristic and the modification of the first buffer size and the second buffer size.
3. The data storage device of claim 2 , wherein the workload characteristic is mapped to a buffer memory profile.
4. The data storage device of claim 3 , wherein the buffer memory profile defines the first buffer size, the second buffer size and the third buffer size.
5. The data storage device of claim 4 , wherein modifying the first buffer size, the second buffer size, and the third buffer size is based on the buffer memory profile.
6. The data storage device of claim 5 , wherein the processor is further configured to identify a second workload characteristic and map the second workload characteristic to a second buffer memory profile.
7. A controller for a data storage device, comprising:
a buffer memory device comprising a first buffer partition comprising one of a transactional random access memory (TRAM) buffer, a logical to physical cache (L2P) buffer, or a parity random access memory (XRAM) buffer, the first buffer partition being of a first buffer size, and a second buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer that is different from the first buffer partition, the of a second buffer partition being of a second buffer size, the first buffer size and second buffer size allocated based on a first workload, wherein the buffer memory device is a contiguous physical memory space, wherein a TRAM buffer is a holding buffer for write operations and relocation operations, wherein an L2P buffer is buffer space for storing parts of a logical to physical table mapping logical location references to physical locations on the NVM device, and wherein an XRAM buffer is configured to hold parity data accumulated for different pages of each open block of the NVM device; and
a buffer management module (BMG) coupled to the buffer memory, configured to adjust the first buffer size and second buffer size based on a second workload of the data storage device.
8. The controller of claim 7 , wherein the BMG being configured to adjust comprises:
identifying a workload characteristic of the second workload;
modifying the first buffer size; and
modifying the second buffer size based on the modification of the first buffer size.
9. The controller of claim 8 , wherein the identified workload characteristic of the second workload is mapped to a buffer memory profile.
10. The controller of claim 9 , wherein the buffer memory profile defines the first buffer size and the second buffer size.
11. The controller of claim 10 , wherein the first buffer size and second buffer size is modified based on the buffer memory profile.
12. The controller of claim 11 , wherein the BMG adjusts the first buffer size and second buffer size based on a third workload that is mapped to a second buffer memory profile.
13. The controller of claim 10 , wherein the buffer memory further comprises a third buffer partition comprising one of a TRAM buffer, an L2P buffer, or an XRAM buffer, that is different than the first buffer partition and second buffer partition, the third buffer partition being of a third buffer size, and wherein the BMG adjusts the third buffer size based on the second workload.
14. The controller of claim 13 , wherein the first buffer partition comprises a TRAM buffer, the second buffer partition comprises an XRAM buffer, and the third buffer partition comprises an L2P buffer.
15. A data storage device, comprising:
one or more non-volatile memory (NVM) means; and
a controller comprising computer-readable instructions that cause the controller to:
identify a workload characteristic of a workload of the data storage device;
remove a first data type from a first buffer partition of a buffer memory means based on the workload characteristic;
modify a first buffer size; and
modify a second buffer size of a second buffer partition of the buffer memory means, based on the modification of the first buffer size, wherein the first buffer partition comprises one of a transactional random access memory (TRAM) buffer, a logical to physical cache (L2P) buffer, or a parity random access memory (XRAM) buffer, wherein the second buffer partition comprises one of a TRAM buffer, an L2P buffer, or an XRAM buffer that is different from the first buffer partition, wherein the buffer memory device is a contiguous physical memory space, wherein a TRAM buffer is a holding buffer for write operations and relocation operations, wherein an L2P buffer is buffer space for storing parts of a logical to physical table mapping logical location references to physical locations on the NVM device, and wherein an XRAM buffer is configured to hold parity data accumulated for different pages of each open block of the NVM device.
16. The data storage device of claim 15 , wherein the workload characteristic is mapped to a buffer memory profile.
17. The data storage device of claim 16 , wherein the buffer memory profile defines the first buffer size and the second buffer size.
18. The data storage device of claim 17 , wherein modifying the first buffer size and second buffer size is based on the buffer memory profile.
19. The data storage device of claim 18 , wherein the computer-readable instructions further cause the controller to identify a second workload characteristic of a second workload, mapping the second workload characteristic to a second buffer memory profile, and modifying the first buffer size and second buffer size based on the second buffer memory profile.
20. The data storage device of 16 , wherein the TRAM buffer is managed in 4 KB increments.