Interrupt coalescing protection logic
A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.
1. A data storage device, comprising:
one or more non-volatile memory devices; and
a controller coupled to the one or more non-volatile memory devices, wherein the controller comprises interrupt coalescing protection logic configured to:
determine that either a head pointer, a tail pointer, or both the head pointer and the tail pointer of a completion queue have changed;
reset a timer based on the determining;
detect that the head pointer or the tail pointer in the completion queue has not changed for a predetermined period of time, wherein the timer measures a period of time that the head pointer and the tail pointer have not changed; and
post an interrupt to a host device.
2. The data storage device of claim 1 , wherein the predetermined period of time is a dynamic period of time.
3. The data storage device of claim 2 , wherein the dynamic period of time is based on one or more host device characteristics.
4. The data storage device of claim 2 , wherein the dynamic period of time is based on a completion queue depth.
5. The data storage device of claim 2 , wherein the dynamic period of time is based on an application type requested in a command from the host device.
6. The data storage device of claim 1 , wherein the predetermined period of time is a fixed period of time.
7. The data storage device of claim 1 , wherein the interrupt coalescing protection logic is further configured to:
detect a change in either the head pointer or the tail pointer; and
reset a timer tracking the predetermined period of time.
8. The data storage device of claim 1 , wherein the interrupt coalescing protection logic is further configured to:
determine that the head pointer is equal to the tail pointer; and
inactivate a timer tracking the predetermined period of time.
9. The data storage device of claim 1 , wherein the interrupt coalescing protection logic is further configured to perform adaptive and dynamic interrupt coalescing.
10. The data storage device of claim 9 , wherein the adaptive and dynamic interrupt coalescing is independent of the interrupt coalescing protection logic.
11. The data storage device of claim 1 , wherein the completion queue is disposed on a host device, wherein the host device comprises a plurality of completion queues, and wherein each completion queue comprises separate interrupt coalescing protection logic disposed in the controller.
12. A data storage device, comprising:
one or more non-volatile memory devices; and
a controller coupled to the one or more non-volatile memory devices, wherein the controller comprises interrupt coalescing protection logic configured to:
determine whether a head pointer, a tail pointer, or both the head pointer and the tail pointer of a completion queue have changed;
move between a state where a timer is active, the timer is reset, and the timer is inactive, wherein the state of the timer is based on the determining, and
wherein the timer measures a period of time that the head pointer and the tail pointer have not changed; and
post an interrupt to a host device after the timer is active and a timeout has occurred.
13. The data storage device of claim 12 , wherein the interrupt coalescing protection logic is further configured to move the timer to an inactive state after posting the interrupt.
14. The data storage device of claim 12 , wherein the interrupt coalescing protection logic is further configured to move the timer to a reset state upon determining a change in the head pointer or the tail pointer of a completion queue.
15. The data storage device of claim 14 , wherein the interrupt coalescing protection logic is further configured to move the timer to an active state upon determining that the head pointer is not equal to the tail pointer.
16. The data storage device of claim 15 , wherein the interrupt coalescing protection logic is further configured to move the timer to an inactive state upon determining that the head pointer is equal to the tail pointer when the timer is reset.
17. The data storage device of claim 16 , wherein the interrupt coalescing protection logic is further configured to move the timer to the reset state upon detecting a change in either the head pointer or the tail pointer.
18. The data storage device of claim 14 , wherein the interrupt coalescing protection logic is further configured to move the timer to an inactive state upon determining that the head pointer is equal to the tail pointer when the timer is active.
19. A data storage device, comprising:
one or more non-volatile memory means; and
a controller coupled to the one or more non-volatile memory means, wherein the controller is configured to:
perform adaptive and dynamic interrupt coalescing; and
post an interrupt to a host device based on a timer, wherein the timer is reset when either a head pointer, a tail pointer, or both the head pointer and the tail pointer of a completion queue have changed, and wherein the timer measures a period of time that the head pointer and the tail pointer have not changed.
20. The data storage device of claim 19 , wherein a number of times that the controller is configured to post the interrupt to the host device based on the timer is equal to a number of completion queues in the host device.