Flash memory controller and associated control method
The present invention provides a control method of a flash memory controller, which includes the steps of: setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time; receiving multiple commands from a submission queue in a host device, generating multiple command responses after processing the multiple commands, and writing the multiple command responses to a completion queue in the host device; receiving a submission queue tail and a completion queue head from the host device; and when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue of the host device.
1. A flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory controller comprises:
a read-only memory (ROM), configured to store a program code;
a microprocessor, configured to execute the program code to control access of the flash memory module;
wherein the microprocessor is configured to perform the steps of:
setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time;
receiving multiple commands from a submission queue in a host device, processing the multiple commands to generate multiple command responses respectively, and writing the multiple command responses to a completion queue in the host device;
receiving a submission queue tail and a completion queue head from the host device, wherein the submission queue tail indicates how many commands the host device sends, and the completion queue head indicates how many command responses the host device has read from the completion queue;
when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue inside the host device; and
when the timer reaches the timeout value, sending an interrupt signal to the host device, wherein the interrupt signal is used to trigger the host device to read the multiple command responses from the completion queue.
2. The flash memory controller of claim 1 , wherein the waiting time in the interrupt coalescing mechanism is greater than a time required for the microprocessor to complete execution of multiple read commands or multiple write commands.
3. The flash memory controller of claim 1 , wherein the step of when the timer reaches the timeout value, sending the interrupt signal to the host device comprises:
sending the interrupt signal to the host device only when the timer reaches the timeout value; and before the timer reaches the timeout value, no interrupt signal is sent to the host device.
4. The flash memory controller of claim 1 , wherein the step of when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain the queue depth of the command queue inside the host device comprises:
when the timer reaches the timeout value, controlling a queue depth calculation circuit to subtract the completion queue head from the submission queue tail to obtain the queue depth of the command queue inside the host device.
5. The flash memory controller of claim 1 , wherein the microprocessor is further configured to perform the steps of:
controlling a time for the microprocessor to send the interrupt signal to the host device when processing subsequent commands based on the calculated queue depth of the command queue.
6. A control method of a flash memory controller, comprising:
setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time;
receiving multiple commands from a submission queue in a host device, processing the multiple commands to generate multiple command responses respectively, and writing the multiple command responses to a completion queue in the host device;
receiving a submission queue tail and a completion queue head from the host device, wherein the submission queue tail indicates how many commands the host device sends, and the completion queue head indicates how many command responses the host device has read from the completion queue;
when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue inside the host device; and
when the timer reaches the timeout value, sending an interrupt signal to the host device, wherein the interrupt signal is used to trigger the host device to read the multiple command responses from the completion queue.
7. The control method of claim 6 , wherein the waiting time in the interrupt coalescing mechanism is greater than a time required for the flash memory controller to complete execution of multiple read commands or multiple write commands.
8. The control method of claim 6 , wherein the step of when the timer reaches the timeout value, sending the interrupt signal to the host device comprises:
sending the interrupt signal to the host device only when the timer reaches the timeout value; and before the timer reaches the timeout value, no interrupt signal is sent to the host device.
9. The control method of claim 6 , wherein the step of when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain the queue depth of the command queue inside the host device comprises:
when the timer reaches the timeout value, controlling a queue depth calculation circuit to subtract the completion queue head from the submission queue tail to obtain the queue depth of the command queue inside the host device.
10. The control method of claim 6 , wherein the microprocessor is further configured to perform the steps of:
controlling a time for the flash memory controller to send the interrupt signal to the host device when processing subsequent commands based on the calculated queue depth of the command queue.