IP Library Granted Patent US 11,868,662
Granted Patent B2
US 11,868,662 · App. 17/752,470 · Granted Jan 9, 2024

Storage system and method for hybrid mapping

Inventors: Ran Zamir (Ramat Gan, IL); Alexander Bazarsky (Holon, IL); David Avraham (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0607G06F3/0622G06F3/0679
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Quick Facts
Patent No.
US 11,868,662
App. No.
17/752,470
Granted
Jan 9, 2024
Kind
B2
Abstract

A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.

Claims (27)

1. In a host coupled with a storage system comprising a non-volatile memory, a method comprising:

creating a plurality of memory mappings that translate data bits into different physical voltage levels in the non-volatile memory, wherein the plurality of mappings are created according to host-defined namespaces;

determining an expected workload of an application in the host; and

sending, to the storage system, a selection of one of the plurality of memory mappings based on the expected workload, wherein the plurality of mappings comprises (i) a separable binary mapping (SBM) used for cache workloads and (ii) at least one mapping for a respective at least one other type of workload.

2. The method of claim 1 , wherein the plurality of mappings are created based on a user-defined command.

3. The method of claim 1 , wherein the plurality of mappings are used for a key-value data structure.

4. The method of claim 3 , wherein the plurality of mappings are configured. according to a key-value format.

5. The method of claim 3 , wherein the plurality of mappings are configured according to a key-value size.

6. A storage system comprising:

a non-volatile memory, wherein the storage system supports a plurality of memory mappings that translate data bits into different physical voltage levels in the non-volatile memory, wherein the plurality of mappings are created according to host-defined namespaces and comprises (i) a separable binary mapping (SBM) used for cache workloads and (ii) at least one mapping for a respective at least one other type of workload;

means for receiving, from a host, a selection of one of the plurality of memory mappings, wherein the selection is based on a host application or a workload expected by the host; and

means for using the selected memory mapping for a memory access operation.

7. A storage system comprising:

a non-volatile memory, wherein the storage system supports a plurality of memory mappings that translate data bits into different physical voltage levels in the non-volatile memory; and

a controller coupled with the non-volatile memory and configured to:

receive, from a host, a selection of one of the plurality of memory mappings, wherein:

the selection is based on an application or expected workload of the host;

the plurality of mappings are created according to host-defined namespaces;

the plurality of mappings comprises (i) a separable binary mapping (SBM) used for cache workloads and (ii) at least one mapping for a respective at least one other type of workload; and

use the selected memory mapping for a memory access operation.

8. The storage system of claim 7 , wherein the plurality of mappings are selected based on a user-defined command.

9. The storage system of claim 7 , wherein the plurality of mappings are used for a key-value data structure.

10. The storage system of claim 9 , wherein the plurality of mappings are configured according to a key-value format.

11. The storage system of claim 9 , wherein the plurality of mappings are configured according to a key-value size.

12. The storage system of claim 7 , wherein the plurality of mappings are created by the host.

13. The storage system of claim 7 , wherein the plurality of mappings are created by the storage system.

14. The storage system of claim 7 , wherein the non-volatile memory comprises a three-dimensional memory.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: ZAMIR, RAN; BAZARSKY, ALEXANDER; AVRAHAM, DAVID
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060006/0102 →
Continuity (1)
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